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charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Thanks for your answer, do you know if the working ones return actual or = random numbers=3F And do you know if it is easily possible to implement the actual behavior= of other counters=3F Regards, Elio Il 4 dic 2023, 9:30=E2=80=AFAM +0100, Atish Patra , ha scritto: > On =46ri, Dec 1, 2023 at 7:57=E2=80=AFAM ELIO VINCIGUERRA > wrote: > > > > Hi everybody, I recently started using RISCV architectures, I would n= eed a way to access =E2=80=9Chpmcounter=5B3-31=5D=E2=80=9D registers usin= g QEMU emulator. > > > > The kernel used for simulations is a C program, not a heavy operating= system, which is why I would need to access the registers mentioned befo= re via assembly. > > > > Trivially accessing any of those registers always returns zero. > > > > The question is: > > Are these registers enabled in QEMU=3F If not, is it possible to enab= le them or are they hardwired to zero=3F How=3F > > > > Trying to access the registers =E2=80=9Ccycle=E2=80=9D, =E2=80=9Cinst= ret=E2=80=9D and =E2=80=9Ctime=E2=80=9D the values come out to be non-zer= o, which is why I think it is also possible to enable =E2=80=9Chpmcounter= =5B3-31=5D=E2=80=9D, but the mode of operation is unknown to me, can anyo= ne help me=3F > > > > Yes. You can use all the hpmcounters=5B3-31=5D. By default, > hpmcounter=5B3-18=5D are enabled. You can modify the set of counters us= ing > pmu-mask cpu property. > https://gitlab.com/qemu-project/qemu/-/blob/master/target/riscv/cpu.c=3F= ref=5Ftype=3Dheads=23L1467 > > However, upstream Qemu doesn't support a lot of PMU events. It only > supports 3 cache related events apart from cycle/instret. > > Here are the events it supports. > https://gitlab.com/qemu-project/qemu/-/blob/master/target/riscv/pmu.c=3F= ref=5Ftype=3Dheads=23L36 > > > Regards, > > Elio > > > > -- > Regards, > Atish --656f1dfe_34fef653_1fd Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline
Thanks for your answer, do you know if the working = ones return actual or random numbers=3F

And do you know if it is easily possible to implement the actual behavior= of other counters=3F

Regards,
Elio
Il 4 dic 2023, 9:30=E2=80=AFAM +010= 0, Atish Patra <atishp=40atishpatra.org>, ha scritto:
On =46ri, Dec 1, 2023 at 7:57=E2=80=AFAM ELIO VINCIGUERRA
= <elio.vinciguerra=40phd.unict.it> wrote:

Hi everybody, I recently started using RISCV architectures, I would need = a way to access =E2=80=9Chpmcounter=5B3-31=5D=E2=80=9D registers using QE= MU emulator.

The kernel used for simulations is a C program, not a heavy operating sys= tem, which is why I would need to access the registers mentioned before v= ia assembly.

Trivially accessing any of those registers always returns zero.

The question is:
Are these registers enabled in QEMU=3F If not, is it possible to enable t= hem or are they hardwired to zero=3F How=3F

Trying to access the registers =E2=80=9Ccycle=E2=80=9D, =E2=80=9Cinstret=E2= =80=9D and =E2=80=9Ctime=E2=80=9D the values come out to be non-zero, whi= ch is why I think it is also possible to enable =E2=80=9Chpmcounter=5B3-3= 1=5D=E2=80=9D, but the mode of operation is unknown to me, can anyone hel= p me=3F


Yes. You can use all the hpmcounters=5B3-31=5D. By default,
hpmcounter=5B3-18=5D are enabled. You can modify the set of counters usin= g
pmu-mask cpu property.
https://gitlab.com/qemu-project/qemu/-/blob/master/target/riscv/cpu.c=3Fr= ef=5Ftype=3Dheads=23L1467

However, upstream Qemu doesn't support a lot of PMU events. It only
= supports 3 cache related events apart from cycle/instret.

Here are the events it supports.
https://gitlab.com/qemu-project/qemu/-/blob/master/target/riscv/pmu.c=3Fr= ef=5Ftype=3Dheads=23L36

Regards,
Elio



--
Regards,
Atish
--656f1dfe_34fef653_1fd--