From mboxrd@z Thu Jan 1 00:00:00 1970 From: Martyn Welch Date: Tue, 09 Apr 2019 09:49:07 +0100 Subject: [U-Boot] [PATCH] imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM In-Reply-To: <6405a060-6214-47fc-a520-7fac73c781de@gmail.com> References: <20190407175654.2924091-1-parthitce@gmail.com> <7e6b830a02c34d9df57f49a61210db8012e220ef.camel@collabora.com> <6405a060-6214-47fc-a520-7fac73c781de@gmail.com> Message-ID: <6280cf7718d07ec7d85d764f409a0082c48739d4.camel@collabora.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On Mon, 2019-04-08 at 20:04 +0200, Parthiban wrote: > Hello Martyn, > > On 4/8/19 7:45 PM, Martyn Welch wrote: > > On Sun, 2019-04-07 at 19:56 +0200, Parthiban Nallathambi wrote: > > > diff --git a/board/phytec/pcl063/spl.c > > > b/board/phytec/pcl063/spl.c > > > index b93cd493f2..73a774645d 100644 > > > --- a/board/phytec/pcl063/spl.c > > > +++ b/board/phytec/pcl063/spl.c > > > @@ -13,6 +13,7 @@ > > > #include > > > #include > > > #include > > > +#include > > > #include > > > > > > /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 > > > -> > > > 256MiB */ > > > @@ -117,11 +118,32 @@ static iomux_v3_cfg_t const usdhc1_pads[] = > > > { > > > MX6_PAD_UART1_RTS_B__USDHC1_CD_B | > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > > }; > > > > > > +#ifndef CONFIG_NAND_MXS > > > +static iomux_v3_cfg_t const usdhc2_pads[] = { > > > + MX6_PAD_NAND_RE_B__USDHC2_CLK | > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > > + MX6_PAD_NAND_WE_B__USDHC2_CMD | > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > > + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > > + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > > + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > > + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > > + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > > + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > > + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > > + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | > > > MUX_PAD_CTRL(USDHC_PAD_CTRL), > > > +}; > > > +#endif > > > + > > > > Umm, these pins are already used a few lines up for the NAND, via > > gpmi: > > I understand. But pcl063 can't co-exit with NAND and eMMC together. I > comes > either with eMMC or NAND. Opps, sorry, just realised that I added this comment in the wrong place. This is in relation to the following being added to pcl063-common.dtsi: + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; If there exists pcl063 modules that have eMMC and others that have NAND using the same pins, then this configuration is not common and therefore shouldn't be in pcl063-common.dtsi. Is it dependent on the flavour of i.MX used? If so I'd suggest the gpmi config needs to be pulled out into imx6ul-phycore-segin.dts and the usdhc2 config needs to be in imx6ull-phycore-segin.dts. > > > pinctrl_gpmi_nand: gpminandgrp { > > fsl,pins = < > > MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0 > > b0b1 > > MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0 > > b0b1 > > MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0 > > b0b1 > > MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B > > 0x0b000 > > MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0 > > b0b1 > > MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0 > > b0b1 > > MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0 > > b0b1 > > MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0 > > b0b1 > > MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0 > > b0b1 > > MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0 > > b0b1 > > MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0 > > b0b1 > > MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0 > > b0b1 > > MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0 > > b0b1 > > MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0 > > b0b1 > > MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0 > > b0b1 > > >; > > }; > > > > > static struct fsl_esdhc_cfg usdhc_cfg[] = { > > > { > > > .esdhc_base = USDHC1_BASE_ADDR, > > > .max_bus_width = 4, > > > }, > > > +#ifndef CONFIG_NAND_MXS > > > + { > > > + .esdhc_base = USDHC2_BASE_ADDR, > > > + .max_bus_width = 8, > > > + }, > > > +#endif > > > }; > > > > > > int board_mmc_getcd(struct mmc *mmc) > > > @@ -131,12 +153,58 @@ int board_mmc_getcd(struct mmc *mmc) > > > > > > int board_mmc_init(bd_t *bis) > > > { > > > - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, > > > ARRAY_SIZE(usdhc1_pads)); > > > - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); > > > - > > > - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); > > > + int i, ret; > > > + > > > + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { > > > > This breaks for the existing phycore_pcl063_defconfig: > > Ah, I missed it. I will add CONFIG_SYS_FSL_USDHC_NUM to 1 in > phycore_pcl063_defconfig. > > Thanks, > Parthiban N > > > board/phytec/pcl063/spl.c: In function ‘board_mmc_init’: > > board/phytec/pcl063/spl.c:158:18: error: ‘CONFIG_SYS_FSL_USDHC_NUM’ > > undeclared (first use in this function); did you mean > > ‘CONFIG_SYS_FSL_ESDHC_ADDR’? > > for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { > > ^~~~~~~~~~~~~~~~~~~~~~~~ > > > > > > Martyn > > > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > https://lists.denx.de/listinfo/u-boot