Re: [PATCH v9 11/12] KVM: x86/pmu: Reject writes to reserved MSR_PERF_METRICS bits

["Mi, Dapeng" <dapeng1.mi@linux.intel.com>]

LGTM. Thanks.

Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>

On 9/19/2026 3:39 AM, Zide Chen wrote:
> When the host CPU supports only 4 Topdown metrics, bits [63:32] of
> MSR_PERF_METRICS are reserved.
>
> Derive pmu->perf_metrics_rsvd from the number of supported Topdown
> metrics and use it to validate writes. Reject any attempts to set
> reserved bits in MSR_PERF_METRICS.
>
> Signed-off-by: Zide Chen <zide.chen@intel.com>
> ---
> v9: new patch.
> ---
>  arch/x86/include/asm/kvm_host.h |  1 +
>  arch/x86/kvm/pmu.c              |  1 +
>  arch/x86/kvm/vmx/pmu_intel.c    | 18 +++++++++++++++++-
>  3 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index 052bf377dedb..31454ecee371 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -585,6 +585,7 @@ struct kvm_pmu {
>  	u64 reserved_bits;
>  	u64 raw_event_mask;
>  	u64 perf_metrics;
> +	u64 perf_metrics_rsvd;
>  	struct kvm_pmc gp_counters[KVM_MAX_NR_GP_COUNTERS];
>  	struct kvm_pmc fixed_counters[KVM_MAX_NR_FIXED_COUNTERS];
>  
> diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
> index 0df283a169b6..41f2d31c495f 100644
> --- a/arch/x86/kvm/pmu.c
> +++ b/arch/x86/kvm/pmu.c
> @@ -1006,6 +1006,7 @@ void kvm_pmu_refresh(struct kvm_vcpu *vcpu)
>  	pmu->fixed_ctr_ctrl_rsvd = ~0ull;
>  	pmu->pebs_enable_rsvd = ~0ull;
>  	pmu->pebs_data_cfg_rsvd = ~0ull;
> +	pmu->perf_metrics_rsvd = ~0ull;
>  	bitmap_zero(pmu->all_valid_pmc_idx, X86_PMC_IDX_MAX);
>  
>  	if (!vcpu->kvm->arch.enable_pmu)
> diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> index fab0891ad46a..98e2fb80347a 100644
> --- a/arch/x86/kvm/vmx/pmu_intel.c
> +++ b/arch/x86/kvm/vmx/pmu_intel.c
> @@ -417,6 +417,9 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>  			reprogram_fixed_counters(pmu, data);
>  		break;
>  	case MSR_PERF_METRICS:
> +		if (data & pmu->perf_metrics_rsvd)
> +			return 1;
> +
>  		pmu->perf_metrics = data;
>  		break;
>  	case MSR_IA32_PEBS_ENABLE:
> @@ -601,9 +604,22 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
>  	counter_rsvd = ~((BIT_ULL(pmu->nr_arch_gp_counters) - 1) |
>  			 ((BIT_ULL(pmu->nr_arch_fixed_counters) - 1) << KVM_FIXED_PMC_BASE_IDX));
>  	pmu->global_ctrl_rsvd = counter_rsvd;
> -	if (perf_capabilities & PERF_CAP_PERF_METRICS)
> +	if (perf_capabilities & PERF_CAP_PERF_METRICS) {
>  		pmu->global_ctrl_rsvd &= ~GLOBAL_CTRL_EN_PERF_METRICS;
>  
> +		/*
> +		 * PERF_METRICS has one 8-bit field per metric. At 8 metrics,
> +		 * skip computing the mask and set perf_metrics_rsvd to 0
> +		 * directly, since BIT_ULL(64) is undefined.
> +		 */
> +		if (kvm_pmu_cap.num_topdown_events < INTEL_TD_METRIC_NUM)
> +			pmu->perf_metrics_rsvd =
> +				~(BIT_ULL(kvm_pmu_cap.num_topdown_events *
> +					  INTEL_TD_METRIC_FIELD_BITS) - 1);
> +		else
> +			pmu->perf_metrics_rsvd = 0;
> +	}
> +
>  	/*
>  	 * GLOBAL_STATUS and GLOBAL_OVF_CONTROL (a.k.a. GLOBAL_STATUS_RESET)
>  	 * share reserved bit definitions.  The kernel just happens to use