From: Alejandro Vallejo <alejandro.vallejo@cloud.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Xen-devel <xen-devel@lists.xenproject.org>,
"Wei Liu" <wl@xen.org>,
"Anthony PERARD" <anthony.perard@citrix.com>,
"Juergen Gross" <jgross@suse.com>,
"Jan Beulich" <jbeulich@suse.com>,
"Roger Pau Monné" <roger.pau@citrix.com>
Subject: Re: [PATCH v2 1/3] x86: Add bit definitions for Automatic IBRS
Date: Wed, 31 May 2023 09:42:13 +0100 [thread overview]
Message-ID: <64770866.050a0220.c32a7.5357@mx.google.com> (raw)
In-Reply-To: <bc209116-75ac-06d6-e4bb-eb77b10ac5bd@citrix.com>
On Tue, May 30, 2023 at 06:29:14PM +0100, Andrew Cooper wrote:
> ... I've changed this on commit to just "Automatic IBRS". The behaviour
> is more far complicated than this, and anyone who wants to know needs to
> read the manual extra carefully.
>
> For one, there's a behaviour which depends on whether SEV-SNP was
> enabled in firmware...
>
> ~Andrew
Ack.
Alejandro
next prev parent reply other threads:[~2023-05-31 8:42 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-30 13:58 [PATCH v2 0/3] Add Automatic IBRS support Alejandro Vallejo
2023-05-30 13:58 ` [PATCH v2 1/3] x86: Add bit definitions for Automatic IBRS Alejandro Vallejo
2023-05-30 17:29 ` Andrew Cooper
2023-05-31 8:42 ` Alejandro Vallejo [this message]
2023-05-30 13:58 ` [PATCH v2 2/3] x86: Expose Automatic IBRS to guests Alejandro Vallejo
2023-05-30 17:31 ` Andrew Cooper
2023-05-31 9:01 ` Alejandro Vallejo
2023-05-31 12:38 ` Andrew Cooper
2023-05-30 13:58 ` [PATCH v2 3/3] x86: Add support for AMD's Automatic IBRS Alejandro Vallejo
2023-06-01 10:35 ` Jan Beulich
2023-06-01 10:36 ` Andrew Cooper
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