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From: Dmitry Osipenko <digetx@gmail.com>
To: Sowjanya Komatineni <skomatineni@nvidia.com>,
	Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>,
	Mantravadi Karthik <mkarthik@nvidia.com>,
	Shardar Mohammed <smohammed@nvidia.com>,
	Timo Alho <talho@nvidia.com>,
	"linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-i2c@vger.kernel.org" <linux-i2c@vger.kernel.org>
Subject: Re: [PATCH V12 3/5] i2c: tegra: Add DMA support
Date: Wed, 6 Feb 2019 17:24:55 +0300	[thread overview]
Message-ID: <649cdfb4-214e-bf01-348d-f950628ecf9b@gmail.com> (raw)
In-Reply-To: <BYAPR12MB3398D7685B5A7462161F9578C26F0@BYAPR12MB3398.namprd12.prod.outlook.com>

06.02.2019 17:19, Sowjanya Komatineni пишет:
>>>>> No, there are no timeout errors in PIO mode. I could post full log with the PIO-only mode if you want.
>>>>>
>>>> Yes please post full log of PIO only and DMA only Also, in above log, 
>>>> lots of DMA transfer went thru fine except this one transfer where 
>>>> DMA timed out.
>>>> DMA completion doesnt happen on DMA submit during this particular 
>>>> transaction timeframe for some reason.
>>>
>>> Dmitry, can you provide some background information on the setup that 
>>> you're using? I vaguely remember something about i2c@7000d000 being 
>>> special on older Tegra devices. Perhaps there's something additional 
>>> that we need to take into account?
>>>
>>> Aha! Look at tegra_i2c_reg_addr() which special-cases I2C_TX_FIFO on 
>>> the DVC variant of the controller, which is exactly the one that you 
>>> are seeing the timeouts on and it's exactly the register that we use 
>>> as destination for the DMA transfer.
>>>
>>> I think we need to do something like this:
>>>
>>> 	slv_config.dst_addr = i2c_dev->base_phys + 
>>> tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
>>>
>>> to make sure we pass the right FIFO register address to DMA.
>>
>> I'm running it on T20 at the moment. I don't know about the DVC quirks, but sounds plausible. Please let me know if you need any other info.
>>
>> Here the full logs:
>>
>> PIO-only: http://dpaste.com/2MX3EAN.txt
>> DMA-only: http://dpaste.com/3VXZSSM.txt
>>
>> Note the "Failed to read T44 and T5 (-110)" error that happens in DMA-only. And it happens on i2c@7000c000, DVC is i2c@7000d000.
> 
> Yes this is due to same issue theirry mentioned.
> Prior to transfer timeout for touch, tps6586x regulator probe failed due to i2c timeout which uses DVC (7000D000) and since DMA mode is enforced all DVC/PWR I2C transactions also go thru DMA and FIFO register for DVC offset is not accounted when configure to dma slave.
> Will fix and send so you can see for repro with updated patch..
> 
> 
> [    0.925155] tegra-i2c 7000d000.i2c: starting DMA for length: 16
> [    0.925165] tegra-i2c 7000d000.i2c: unmasked irq: 0c
> [    1.028961] tegra-i2c 7000d000.i2c: i2c transfer timed out
> [    1.028968] tegra-i2c 7000c000.i2c: DMA transfer timeout
> [    1.028995] tps6586x 3-0034: Chip ID read failed: -110
> [    1.029029] tps6586x: probe of 3-0034 failed with error -5
> [    1.029045] atmel_mxt_ts 0-004c: __mxt_read_reg: i2c transfer failed (-110)
> [    1.029051] atmel_mxt_ts 0-004c: Failed to read T44 and T5 (-110)
> 

I think tps6586x and atmel-touch should be independent issues, but will see. Thanks!

  reply	other threads:[~2019-02-06 14:24 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-05 22:46 [PATCH V12 1/5] i2c: tegra: sort all the include headers alphabetically Sowjanya Komatineni
2019-02-05 22:46 ` Sowjanya Komatineni
2019-02-05 22:46 ` [PATCH V12 2/5] i2c: tegra: add bus clear Master Support Sowjanya Komatineni
2019-02-05 22:46   ` Sowjanya Komatineni
2019-02-05 22:46 ` [PATCH V12 3/5] i2c: tegra: Add DMA support Sowjanya Komatineni
2019-02-05 22:46   ` Sowjanya Komatineni
2019-02-06 11:55   ` Dmitry Osipenko
2019-02-06 12:49     ` Sowjanya Komatineni
2019-02-06 13:06       ` Dmitry Osipenko
2019-02-06 12:59     ` Dmitry Osipenko
2019-02-06 13:03       ` Sowjanya Komatineni
2019-02-06 13:05         ` Dmitry Osipenko
2019-02-06 13:17           ` Sowjanya Komatineni
2019-02-06 13:23             ` Dmitry Osipenko
2019-02-06 13:29               ` Sowjanya Komatineni
2019-02-06 13:30                 ` Sowjanya Komatineni
2019-02-06 13:34                   ` Dmitry Osipenko
2019-02-06 13:40                     ` Dmitry Osipenko
2019-02-06 13:09     ` Thierry Reding
2019-02-06 13:13       ` Thierry Reding
2019-02-06 13:18         ` Dmitry Osipenko
2019-02-06 13:25           ` Sowjanya Komatineni
2019-02-06 13:42             ` Dmitry Osipenko
2019-02-06 13:45               ` Sowjanya Komatineni
2019-02-06 13:51                 ` Sowjanya Komatineni
2019-02-06 14:01                   ` Thierry Reding
2019-02-06 14:10                     ` Sowjanya Komatineni
2019-02-06 14:13                     ` Dmitry Osipenko
2019-02-06 14:19                       ` Sowjanya Komatineni
2019-02-06 14:24                         ` Dmitry Osipenko [this message]
2019-02-06 14:29                           ` Sowjanya Komatineni
2019-02-06 14:35                             ` Dmitry Osipenko
2019-02-06 14:48                               ` Sowjanya Komatineni
2019-02-06 12:40   ` Dmitry Osipenko
2019-02-06 12:48     ` Thierry Reding
2019-02-06 13:01       ` Dmitry Osipenko
2019-02-05 22:46 ` [PATCH V12 4/5] i2c: tegra: update transfer timeout Sowjanya Komatineni
2019-02-05 22:46   ` Sowjanya Komatineni
2019-02-05 22:46 ` [PATCH V12 5/5] i2c: tegra: add i2c interface timing support Sowjanya Komatineni
2019-02-05 22:46   ` Sowjanya Komatineni

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