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Thu, 30 Oct 2025 06:19:27 -0700 (PDT) Received: from [192.168.68.110] ([187.101.65.79]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498d097fasm186887595ad.29.2025.10.30.06.19.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 30 Oct 2025 06:19:26 -0700 (PDT) Message-ID: <653e5fcc-c404-474d-89d3-e5ff2f622b9d@ventanamicro.com> Date: Thu, 30 Oct 2025 10:19:23 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] hw/intc/riscv_aplic: Expand inactive source handling for AIA target[i] To: Nikita Novikov , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Alistair Francis , Weiwei Li , Liu Zhiwei References: <20251029-n-novikov-aplic_aia_ro-v1-0-39fec74c918a@syntacore.com> <20251029-n-novikov-aplic_aia_ro-v1-1-39fec74c918a@syntacore.com> From: Daniel Henrique Barboza Content-Language: en-US In-Reply-To: <20251029-n-novikov-aplic_aia_ro-v1-1-39fec74c918a@syntacore.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 10/29/25 4:17 AM, Nikita Novikov wrote: > According to the RISC-V AIA v1.0, section 4.5.2 ("Source configurations"), > register target[i] shall be read-only zero when interrupt source i is inactive > in this domain. A source is inactive if it is delegated to a child domain or > its source mode is INACTIVE. > > The previous implementation only checked SM == INACTIVE. This patch adds > full compliance: > - Return zero on read if D == 1 or SM == INACTIVE > - Ignore writes in both cases > > Fixes: b6f1244678 ("intc/riscv_aplic: Fix target register read when source is inactive") > Signed-off-by: Nikita Novikov > --- Reviewed-by: Daniel Henrique Barboza > hw/intc/riscv_aplic.c | 28 +++++++++++++++++++++++++--- > 1 file changed, 25 insertions(+), 3 deletions(-) > > diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c > index a2041e702245211ba3bcf4334301d7c86272e36f..8c3b16074cd3ca1bc3004cfaaa13f34b8860bd48 100644 > --- a/hw/intc/riscv_aplic.c > +++ b/hw/intc/riscv_aplic.c > @@ -193,6 +193,26 @@ void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr) > #endif > } > > +/* > + * APLIC target[i] must be read-only zero if the source i is inactive > + * in this domain (delegated or SM == INACTIVE) > + */ > +static inline bool riscv_aplic_source_active(RISCVAPLICState *aplic, > + uint32_t irq) > +{ > + uint32_t sc, sm; > + > + if ((irq == 0) || (aplic->num_irqs <= irq)) { > + return false; > + } > + sc = aplic->sourcecfg[irq]; > + if (sc & APLIC_SOURCECFG_D) { > + return false; > + } > + sm = sc & APLIC_SOURCECFG_SM_MASK; > + return sm != APLIC_SOURCECFG_SM_INACTIVE; > +} > + > static bool riscv_aplic_irq_rectified_val(RISCVAPLICState *aplic, > uint32_t irq) > { > @@ -635,7 +655,7 @@ static void riscv_aplic_request(void *opaque, int irq, int level) > > static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size) > { > - uint32_t irq, word, idc, sm; > + uint32_t irq, word, idc; > RISCVAPLICState *aplic = opaque; > > /* Reads must be 4 byte words */ > @@ -703,8 +723,7 @@ static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size) > } else if ((APLIC_TARGET_BASE <= addr) && > (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) { > irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1; > - sm = aplic->sourcecfg[irq] & APLIC_SOURCECFG_SM_MASK; > - if (sm == APLIC_SOURCECFG_SM_INACTIVE) { > + if (!riscv_aplic_source_active(aplic, irq)) { > return 0; > } > return aplic->target[irq]; > @@ -841,6 +860,9 @@ static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value, > } else if ((APLIC_TARGET_BASE <= addr) && > (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) { > irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1; > + if (!riscv_aplic_source_active(aplic, irq)) { > + return; > + } > if (aplic->msimode) { > aplic->target[irq] = value; > } else { >