From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Laurent Pinchart To: kieran.bingham@ideasonboard.com Cc: Laurent Pinchart , dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v2 14/14] drm: rcar-du: Configure DPAD0 routing through last group on Gen3 Date: Tue, 01 Aug 2017 16:51:08 +0300 Message-ID: <6559605.ajX4pK5sJf@avalon> In-Reply-To: References: <20170626181226.29575-1-laurent.pinchart+renesas@ideasonboard.com> <20170626181226.29575-15-laurent.pinchart+renesas@ideasonboard.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-media-owner@vger.kernel.org List-ID: Hi Kieran, On Tuesday 01 Aug 2017 14:46:13 Kieran Bingham wrote: > On 26/06/17 19:12, Laurent Pinchart wrote: > > On Gen3 SoCs DPAD0 routing is configured through the last CRTC group, > > unlike on Gen2 where it is configured through the first CRTC group. Fix > > the driver accordingly. > > > > Fixes: 2427b3037710 ("drm: rcar-du: Add R8A7795 device support") > > Signed-off-by: Laurent Pinchart > > > > --- > > > > drivers/gpu/drm/rcar-du/rcar_du_group.c | 21 ++++++++++++++------- > > 1 file changed, 14 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c > > b/drivers/gpu/drm/rcar-du/rcar_du_group.c index > > 64738fca96d0..2abb2fdd143e 100644 > > --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c > > +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c > > @@ -208,23 +208,30 @@ void rcar_du_group_restart(struct rcar_du_group > > *rgrp) > > int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu) > > { > > + struct rcar_du_group *rgrp; > > + struct rcar_du_crtc *crtc; > > int ret; > > > > if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS)) > > return 0; > > > > - /* RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are > > - * configured in the DEFR8 register of the first group. As this > > function > > - * can be called with the DU0 and DU1 CRTCs disabled, we need to > > enable > > - * the first group clock before accessing the register. > > + /* > > + * RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are > > + * configured in the DEFR8 register of the first group on Gen2 and the > > + * last group on Gen3. As this function can be called with the DU > > + * channels of the corresponding CRTCs disabled, we need to enable the > > + * group clock before accessing the register. > > */ > > > > - ret = clk_prepare_enable(rcdu->crtcs[0].clock); > > + rgrp = &rcdu->groups[DIV_ROUND_UP(rcdu->num_crtcs, 2) - 1]; > > + crtc = &rcdu->crtcs[rgrp->index * 2]; > > I'm not certain I understand how this makes a distinct difference between > G2, and G3. That's because, well, it doesn't :-) > Is rcdu->num_crtcs the distinguishing factor between the SoC's? I'm not sure what I was thinking when I wrote this. I'll send a v3. > > + > > + ret = clk_prepare_enable(crtc->clock); > > if (ret < 0) > > return ret; > > > > - rcar_du_group_setup_defr8(&rcdu->groups[0]); > > + rcar_du_group_setup_defr8(rgrp); > > > > - clk_disable_unprepare(rcdu->crtcs[0].clock); > > + clk_disable_unprepare(crtc->clock); > > > > return 0; > > } -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PATCH v2 14/14] drm: rcar-du: Configure DPAD0 routing through last group on Gen3 Date: Tue, 01 Aug 2017 16:51:08 +0300 Message-ID: <6559605.ajX4pK5sJf@avalon> References: <20170626181226.29575-1-laurent.pinchart+renesas@ideasonboard.com> <20170626181226.29575-15-laurent.pinchart+renesas@ideasonboard.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from galahad.ideasonboard.com (galahad.ideasonboard.com [IPv6:2001:4b98:dc2:45:216:3eff:febb:480d]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9E71C6ED24 for ; Tue, 1 Aug 2017 13:50:57 +0000 (UTC) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: kieran.bingham@ideasonboard.com Cc: linux-renesas-soc@vger.kernel.org, Laurent Pinchart , dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org List-Id: dri-devel@lists.freedesktop.org SGkgS2llcmFuLAoKT24gVHVlc2RheSAwMSBBdWcgMjAxNyAxNDo0NjoxMyBLaWVyYW4gQmluZ2hh bSB3cm90ZToKPiBPbiAyNi8wNi8xNyAxOToxMiwgTGF1cmVudCBQaW5jaGFydCB3cm90ZToKPiA+ IE9uIEdlbjMgU29DcyBEUEFEMCByb3V0aW5nIGlzIGNvbmZpZ3VyZWQgdGhyb3VnaCB0aGUgbGFz dCBDUlRDIGdyb3VwLAo+ID4gdW5saWtlIG9uIEdlbjIgd2hlcmUgaXQgaXMgY29uZmlndXJlZCB0 aHJvdWdoIHRoZSBmaXJzdCBDUlRDIGdyb3VwLiBGaXgKPiA+IHRoZSBkcml2ZXIgYWNjb3JkaW5n bHkuCj4gPiAKPiA+IEZpeGVzOiAyNDI3YjMwMzc3MTAgKCJkcm06IHJjYXItZHU6IEFkZCBSOEE3 Nzk1IGRldmljZSBzdXBwb3J0IikKPiA+IFNpZ25lZC1vZmYtYnk6IExhdXJlbnQgUGluY2hhcnQK PiA+IDxsYXVyZW50LnBpbmNoYXJ0K3JlbmVzYXNAaWRlYXNvbmJvYXJkLmNvbT4KPiA+IC0tLQo+ ID4gCj4gPiAgZHJpdmVycy9ncHUvZHJtL3JjYXItZHUvcmNhcl9kdV9ncm91cC5jIHwgMjEgKysr KysrKysrKysrKystLS0tLS0tCj4gPiAgMSBmaWxlIGNoYW5nZWQsIDE0IGluc2VydGlvbnMoKyks IDcgZGVsZXRpb25zKC0pCj4gPiAKPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vcmNh ci1kdS9yY2FyX2R1X2dyb3VwLmMKPiA+IGIvZHJpdmVycy9ncHUvZHJtL3JjYXItZHUvcmNhcl9k dV9ncm91cC5jIGluZGV4Cj4gPiA2NDczOGZjYTk2ZDAuLjJhYmIyZmRkMTQzZSAxMDA2NDQKPiA+ IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9yY2FyLWR1L3JjYXJfZHVfZ3JvdXAuYwo+ID4gKysrIGIv ZHJpdmVycy9ncHUvZHJtL3JjYXItZHUvcmNhcl9kdV9ncm91cC5jCj4gPiBAQCAtMjA4LDIzICsy MDgsMzAgQEAgdm9pZCByY2FyX2R1X2dyb3VwX3Jlc3RhcnQoc3RydWN0IHJjYXJfZHVfZ3JvdXAK PiA+ICpyZ3JwKQo+ID4gIGludCByY2FyX2R1X3NldF9kcGFkMF92c3AxX3JvdXRpbmcoc3RydWN0 IHJjYXJfZHVfZGV2aWNlICpyY2R1KQo+ID4gIHsKPiA+ICsJc3RydWN0IHJjYXJfZHVfZ3JvdXAg KnJncnA7Cj4gPiArCXN0cnVjdCByY2FyX2R1X2NydGMgKmNydGM7Cj4gPiAgCWludCByZXQ7Cj4g PiAgCQo+ID4gIAlpZiAoIXJjYXJfZHVfaGFzKHJjZHUsIFJDQVJfRFVfRkVBVFVSRV9FWFRfQ1RS TF9SRUdTKSkKPiA+ICAJCXJldHVybiAwOwo+ID4gCj4gPiAtCS8qIFJHQiBvdXRwdXQgcm91dGlu ZyB0byBEUEFEMCBhbmQgVlNQMUQgcm91dGluZyB0byBEVTAvMS8yIGFyZQo+ID4gLQkgKiBjb25m aWd1cmVkIGluIHRoZSBERUZSOCByZWdpc3RlciBvZiB0aGUgZmlyc3QgZ3JvdXAuIEFzIHRoaXMK PiA+IGZ1bmN0aW9uCj4gPiAtCSAqIGNhbiBiZSBjYWxsZWQgd2l0aCB0aGUgRFUwIGFuZCBEVTEg Q1JUQ3MgZGlzYWJsZWQsIHdlIG5lZWQgdG8KPiA+IGVuYWJsZQo+ID4gLQkgKiB0aGUgZmlyc3Qg Z3JvdXAgY2xvY2sgYmVmb3JlIGFjY2Vzc2luZyB0aGUgcmVnaXN0ZXIuCj4gPiArCS8qCj4gPiAr CSAqIFJHQiBvdXRwdXQgcm91dGluZyB0byBEUEFEMCBhbmQgVlNQMUQgcm91dGluZyB0byBEVTAv MS8yIGFyZQo+ID4gKwkgKiBjb25maWd1cmVkIGluIHRoZSBERUZSOCByZWdpc3RlciBvZiB0aGUg Zmlyc3QgZ3JvdXAgb24gR2VuMiBhbmQgdGhlCj4gPiArCSAqIGxhc3QgZ3JvdXAgb24gR2VuMy4g QXMgdGhpcyBmdW5jdGlvbiBjYW4gYmUgY2FsbGVkIHdpdGggdGhlIERVCj4gPiArCSAqIGNoYW5u ZWxzIG9mIHRoZSBjb3JyZXNwb25kaW5nIENSVENzIGRpc2FibGVkLCB3ZSBuZWVkIHRvIGVuYWJs ZSB0aGUKPiA+ICsJICogZ3JvdXAgY2xvY2sgYmVmb3JlIGFjY2Vzc2luZyB0aGUgcmVnaXN0ZXIu Cj4gPiAgCSAqLwo+ID4gCj4gPiAtCXJldCA9IGNsa19wcmVwYXJlX2VuYWJsZShyY2R1LT5jcnRj c1swXS5jbG9jayk7Cj4gPiArCXJncnAgPSAmcmNkdS0+Z3JvdXBzW0RJVl9ST1VORF9VUChyY2R1 LT5udW1fY3J0Y3MsIDIpIC0gMV07Cj4gPiArCWNydGMgPSAmcmNkdS0+Y3J0Y3NbcmdycC0+aW5k ZXggKiAyXTsKPiAKPiBJJ20gbm90IGNlcnRhaW4gSSB1bmRlcnN0YW5kIGhvdyB0aGlzIG1ha2Vz IGEgZGlzdGluY3QgZGlmZmVyZW5jZSBiZXR3ZWVuCj4gRzIsIGFuZCBHMy4KClRoYXQncyBiZWNh dXNlLCB3ZWxsLCBpdCBkb2Vzbid0IDotKQoKPiBJcyByY2R1LT5udW1fY3J0Y3MgdGhlIGRpc3Rp bmd1aXNoaW5nIGZhY3RvciBiZXR3ZWVuIHRoZSBTb0Mncz8KCkknbSBub3Qgc3VyZSB3aGF0IEkg d2FzIHRoaW5raW5nIHdoZW4gSSB3cm90ZSB0aGlzLiBJJ2xsIHNlbmQgYSB2My4KCj4gPiArCj4g PiArCXJldCA9IGNsa19wcmVwYXJlX2VuYWJsZShjcnRjLT5jbG9jayk7Cj4gPiAgCWlmIChyZXQg PCAwKQo+ID4gIAkJcmV0dXJuIHJldDsKPiA+IAo+ID4gLQlyY2FyX2R1X2dyb3VwX3NldHVwX2Rl ZnI4KCZyY2R1LT5ncm91cHNbMF0pOwo+ID4gKwlyY2FyX2R1X2dyb3VwX3NldHVwX2RlZnI4KHJn cnApOwo+ID4gCj4gPiAtCWNsa19kaXNhYmxlX3VucHJlcGFyZShyY2R1LT5jcnRjc1swXS5jbG9j ayk7Cj4gPiArCWNsa19kaXNhYmxlX3VucHJlcGFyZShjcnRjLT5jbG9jayk7Cj4gPiAKPiA+ICAJ cmV0dXJuIDA7Cj4gPiAgfQoKLS0gClJlZ2FyZHMsCgpMYXVyZW50IFBpbmNoYXJ0CgpfX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGlu ZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVl ZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK