From: Alejandro Vallejo <alejandro.vallejo@cloud.com>
To: Xen-devel <xen-devel@lists.xenproject.org>
Cc: "Jan Beulich" <jbeulich@suse.com>,
"Andrew Cooper" <andrew.cooper3@citrix.com>,
"Roger Pau Monné" <roger.pau@citrix.com>, "Wei Liu" <wl@xen.org>
Subject: Re: [PATCH v2] xen/x86: On x2APIC mode, derive LDR from APIC_ID
Date: Tue, 21 Nov 2023 16:29:53 +0000 [thread overview]
Message-ID: <655cdb04.050a0220.8c71d.d7e5@mx.google.com> (raw)
In-Reply-To: <20231121162604.19405-1-alejandro.vallejo@cloud.com>
On Tue, Nov 21, 2023 at 04:26:04PM +0000, Alejandro Vallejo wrote:
> Both Intel and AMD manuals agree that on x2APIC mode, the APIC LDR and ID
> registers are derivable from each other through a fixed formula.
>
> Xen uses that formula, but applies it to vCPU IDs (which are sequential)
> rather than x2APIC_IDs (which are not, at the moment). As I understand it,
> this is an attempt to tightly pack vCPUs into clusters so each cluster has
> 16 vCPUs rather than 8, but this is problematic for OSs that might read the
> x2APIC_ID and internally derive LDR (or the other way around)
Ugh, forgot about Roger's commit message request
>I would replace the underscore from x2APIC ID with a space instead.
Happy for that to happen on commit if the rest looks ok.
Cheers,
Alejandro
next prev parent reply other threads:[~2023-11-21 16:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-21 16:26 [PATCH v2] xen/x86: On x2APIC mode, derive LDR from APIC_ID Alejandro Vallejo
2023-11-21 16:29 ` Alejandro Vallejo [this message]
2023-11-22 13:40 ` Roger Pau Monné
2023-11-22 15:11 ` Alejandro Vallejo
2023-11-22 17:04 ` Roger Pau Monné
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