Re: [PATCH v4 3/4] baseband/fpga_5gnr_fec: add AGX100 support

[Maxime Coquelin <maxime.coquelin@redhat.com>]

On 1/5/24 22:15, Hernan Vargas wrote:
> Add support for new FPGA variant AGX100 (on Arrow Creek N6000).
> 
> Signed-off-by: Hernan Vargas <hernan.vargas@intel.com>
> ---
>   doc/guides/bbdevs/fpga_5gnr_fec.rst           |   76 +-
>   drivers/baseband/fpga_5gnr_fec/agx100_pmd.h   |  273 ++++
>   .../baseband/fpga_5gnr_fec/fpga_5gnr_fec.h    |   12 +-
>   .../fpga_5gnr_fec/rte_fpga_5gnr_fec.c         | 1230 +++++++++++++++--
>   drivers/baseband/fpga_5gnr_fec/vc_5gnr_pmd.h  |    1 -
>   5 files changed, 1459 insertions(+), 133 deletions(-)
>   create mode 100644 drivers/baseband/fpga_5gnr_fec/agx100_pmd.h
> 
> diff --git a/doc/guides/bbdevs/fpga_5gnr_fec.rst b/doc/guides/bbdevs/fpga_5gnr_fec.rst
> index 956dd6bed560..1ae192a86b25 100644
> --- a/doc/guides/bbdevs/fpga_5gnr_fec.rst
> +++ b/doc/guides/bbdevs/fpga_5gnr_fec.rst
> @@ -6,12 +6,13 @@ Intel(R) FPGA 5GNR FEC Poll Mode Driver
>   
>   The BBDEV FPGA 5GNR FEC poll mode driver (PMD) supports an FPGA implementation of a VRAN
>   LDPC Encode / Decode 5GNR wireless acceleration function, using Intel's PCI-e and FPGA
> -based Vista Creek device.
> +based Vista Creek (N3000, referred to as VC_5GNR in the code) as well as Arrow Creek (N6000,
> +referred to as AGX100 in the code).
>   
>   Features
>   --------
>   
> -FPGA 5GNR FEC PMD supports the following features:
> +FPGA 5GNR FEC PMD supports the following BBDEV capabilities:
>   
>   - LDPC Encode in the DL
>   - LDPC Decode in the UL
> @@ -67,10 +68,18 @@ Initialization
>   
>   When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
>   
> +Vista Creek (N3000)
> +
>   .. code-block:: console
>   
>     sudo lspci -vd8086:0d8f
>   
> +Arrow Creek (N6000)
> +
> +.. code-block:: console
> +
> +  sudo lspci -vd8086:5799
> +
>   The physical and virtual functions are compatible with Linux UIO drivers:
>   ``vfio_pci`` and ``igb_uio``. However, in order to work the FPGA 5GNR FEC device firstly needs
>   to be bound to one of these linux drivers through DPDK.
> @@ -78,6 +87,7 @@ to be bound to one of these linux drivers through DPDK.
>   For more details on how to bind the PF device and create VF devices, see
>   :ref:`linux_gsg_binding_kernel`.
>   
> +
>   Configure the VFs through PF
>   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>   
> @@ -100,7 +110,6 @@ parameters defined in ``rte_fpga_5gnr_fec_conf`` structure:
>         uint8_t dl_bandwidth;
>         uint8_t ul_load_balance;
>         uint8_t dl_load_balance;
> -      uint16_t flr_time_out;
>     };
>   
>   - ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and
> @@ -111,12 +120,12 @@ parameters defined in ``rte_fpga_5gnr_fec_conf`` structure:
>   
>   - ``vf_*l_queues_number``: defines the hardware queue mapping for every VF.
>   
> -- ``*l_bandwidth``: in case of congestion on PCIe interface. The device
> -  allocates different bandwidth to UL and DL. The weight is configured by this
> -  setting. The unit of weight is 3 code blocks. For example, if the code block
> -  cbps (code block per second) ratio between UL and DL is 12:1, then the
> -  configuration value should be set to 36:3. The schedule algorithm is based
> -  on code block regardless the length of each block.
> +- ``*l_bandwidth``: Only used for the Vista Creek schedule algorithm in case of
> +  congestion on PCIe interface. The device allocates different bandwidth to UL
> +  and DL. The weight is configured by this setting. The unit of weight is 3 code
> +  blocks. For example, if the code block cbps (code block per second) ratio between
> +  UL and DL is 12:1, then the configuration value should be set to 36:3.
> +  The schedule algorithm is based on code block regardless the length of each block.
>   
>   - ``*l_load_balance``: hardware queues are load-balanced in a round-robin
>     fashion. Queues get filled first-in first-out until they reach a pre-defined
> @@ -126,10 +135,6 @@ parameters defined in ``rte_fpga_5gnr_fec_conf`` structure:
>     If all hardware queues exceeds the watermark, no code blocks will be
>     streamed in from UL/DL code block FIFO.
>   
> -- ``flr_time_out``: specifies how many 16.384us to be FLR time out. The
> -  time_out = flr_time_out x 16.384us. For instance, if you want to set 10ms for
> -  the FLR time out then set this setting to 0x262=610.
> -

This change sounds unrelated. It should be in a dedicated patch with 
Fixes tag set, as it seems it was already not in fpga_5gnr driver before
this series.

>   
>   An example configuration code calling the function ``rte_fpga_5gnr_fec_configure()`` is shown
>   below:
> @@ -154,7 +159,7 @@ below:
>     /* setup FPGA PF */
>     ret = rte_fpga_5gnr_fec_configure(info->dev_name, &conf);
>     TEST_ASSERT_SUCCESS(ret,
> -      "Failed to configure 4G FPGA PF for bbdev %s",
> +      "Failed to configure 5GNR FPGA PF for bbdev %s",

Ditto

>         info->dev_name);
>   
>