From: Jiri Slaby <jirislaby@kernel.org>
To: "James Hilliard" <james.hilliard1@gmail.com>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Andy Shevchenko" <andriy.shevchenko@linux.intel.com>,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>,
"Chen-Yu Tsai" <wens@kernel.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>
Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev
Subject: Re: [PATCH v3 3/4] serial: 8250_dw: configure the Allwinner H616 UART
Date: Tue, 27 Oct 2026 07:16:08 +0100 [thread overview]
Message-ID: <66361595-cbda-413f-9559-9fae22001bbd@kernel.org> (raw)
In-Reply-To: <20261024-submit-h616-uart-fifo-v1-v3-3-286fc1b8c3c1@gmail.com>
On 24. 10. 26, 22:22, James Hilliard wrote:
> H616 has 256-byte transmit and receive FIFOs, but its optional DesignWare
> component parameter register reads as zero. Generic 16550 probing leaves
> the port using the 16-byte FIFO configuration and its trigger-level table.
>
> Keep PORT_16550A and preserve the FIFO size read from firmware by
> uart_read_port_properties(). Use it for the transmit load and derive the
> receive thresholds from the documented 1-byte, quarter-full, half-full
> and FIFO-depth-minus-two mapping. On H616 these are 1, 64, 128 and 254
> bytes; the normal 16550A half-full FCR setting selects 128 bytes.
>
> Serialize trigger changes with termios and hold a runtime PM reference
> while programming FCR, preserving the FIFO contents. Propagate runtime
> resume errors before changing either the FCR shadow or the hardware.
>
> Advertise automatic flow control so CRTSCTS enables MCR.AFCE. The
> DesignWare termios path selects hardware CTS handling, so the capability
> must be present for the corresponding hardware control to be enabled.
>
> Select the fixed configuration through the platform setup callback.
> H616 has debug-divisor and RS485 control registers at the offsets used to
> detect DesignWare hardware RS485 and fractional-divisor support. Avoid
> those probes and retain the BUSY-safe integer divisor hook and software
> RS485 handling.
>
> Use the existing SKIP_SET_RATE quirk to keep the UART clock enabled during
> termios changes. Its clock is a gate on the shared APB2 source, rather than
> an independent baud-rate generator.
>
> Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
> ---
> drivers/tty/serial/8250/8250_dw.c | 75 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 75 insertions(+)
>
> diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
> index 9c171c5775a6..557832254c37 100644
> --- a/drivers/tty/serial/8250/8250_dw.c
> +++ b/drivers/tty/serial/8250/8250_dw.c
> @@ -19,6 +19,7 @@
> #include <linux/io.h>
> #include <linux/lockdep.h>
> #include <linux/module.h>
> +#include <linux/mutex.h>
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/property.h>
> @@ -648,6 +649,73 @@ static void dw8250_setup(struct uart_port *p)
> dw8250_setup_dma(p);
> }
>
> +static unsigned int dw8250_sunxi_rxtrig_bytes(struct uart_port *p, unsigned int trigger)
> +{
> + switch (trigger) {
> + case 0:
> + return 1;
> + case 1:
> + return p->fifosize / 4;
> + case 2:
> + return p->fifosize / 2;
> + default:
> + return p->fifosize - 2;
These constants are counterintuitive. Can you pass the fcr masked,
unshifted and do:
case UART_FCR_TRIGGER_1:
...
case UART_FCR_TRIGGER_4:
...
...
instead?
> + }
> +}
> +
> +static int dw8250_sunxi_get_rxtrig(struct uart_port *p)
> +{
> + struct uart_8250_port *up = up_to_u8250p(p);
> +
> + guard(uart_port_lock_irqsave)(p);
> +
> + return dw8250_sunxi_rxtrig_bytes(p, UART_FCR_R_TRIG_BITS(up->fcr));
Here:
up->fcr & UART_FCR_TRIGGER_MASK
thanks,
--
js
suse labs
next prev parent reply other threads:[~2026-10-27 6:16 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-24 20:22 [PATCH v3 0/4] serial: 8250_dw: describe the Allwinner H616 UART configuration James Hilliard
2026-10-24 20:22 ` [PATCH v3 1/4] serial: 8250_dw: select port setup through platform data James Hilliard
2026-10-24 20:26 ` sashiko-bot
2026-10-27 6:54 ` Andy Shevchenko
2026-10-24 20:22 ` [PATCH v3 2/4] dt-bindings: serial: snps-dw-apb-uart: add Allwinner H616 James Hilliard
2026-10-24 20:26 ` sashiko-bot
2026-10-27 8:02 ` Krzysztof Kozlowski
2026-10-27 9:39 ` James Hilliard
2026-10-27 9:56 ` Krzysztof Kozlowski
2026-10-27 10:02 ` Chen-Yu Tsai
2026-10-27 10:04 ` Krzysztof Kozlowski
2026-10-27 22:25 ` James Hilliard
2026-10-24 20:22 ` [PATCH v3 3/4] serial: 8250_dw: configure the Allwinner H616 UART James Hilliard
2026-10-24 20:32 ` sashiko-bot
2026-10-27 6:16 ` Jiri Slaby [this message]
2026-10-27 7:21 ` Andy Shevchenko
2026-10-27 7:25 ` Andy Shevchenko
2026-10-24 20:22 ` [PATCH v3 4/4] arm64: dts: allwinner: h616: describe the UART integration and FIFO size James Hilliard
2026-10-24 20:29 ` sashiko-bot
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