Re: [PATCH v9 2/2] cxl: documentation: add missing files to cxl driver-api

[Ira Weiny <ira.weiny@intel.com>]

Yao Xingtao wrote:
> Add the missing files into cxl driver api and fix the compile warning.
> 
> Suggested-by: Dan Williams <dan.j.williams@intel.com>
> Suggested-by: Alison Schofield <alison.schofield@intel.com>
> Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>

Patch looks good.  But I think linux-doc should have been CC'ed as well.

Also, This should have been sent as a stand alone patch so Dave can pick
it up separate from the interleave fix.  I think he can pick it out from
here this time.

Reviewed-by: Ira Weiny <ira.weiny@intel.com>

> ---
>  Documentation/driver-api/cxl/memory-devices.rst | 15 +++++++++++++++
>  drivers/cxl/cxlmem.h                            | 11 ++++++-----
>  2 files changed, 21 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst
> index 5149ecdc53c7..d732c42526df 100644
> --- a/Documentation/driver-api/cxl/memory-devices.rst
> +++ b/Documentation/driver-api/cxl/memory-devices.rst
> @@ -328,6 +328,12 @@ CXL Memory Device
>  .. kernel-doc:: drivers/cxl/mem.c
>     :doc: cxl mem
>  
> +.. kernel-doc:: drivers/cxl/cxlmem.h
> +   :internal:
> +
> +.. kernel-doc:: drivers/cxl/core/memdev.c
> +   :identifiers:
> +
>  CXL Port
>  --------
>  .. kernel-doc:: drivers/cxl/port.c
> @@ -341,6 +347,15 @@ CXL Core
>  .. kernel-doc:: drivers/cxl/cxl.h
>     :internal:
>  
> +.. kernel-doc:: drivers/cxl/core/hdm.c
> +   :doc: cxl core hdm
> +
> +.. kernel-doc:: drivers/cxl/core/hdm.c
> +   :identifiers:
> +
> +.. kernel-doc:: drivers/cxl/core/cdat.c
> +   :identifiers:
> +
>  .. kernel-doc:: drivers/cxl/core/port.c
>     :doc: cxl core
>  
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index 7806194d2de1..af8169ccdbc0 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -395,9 +395,9 @@ enum cxl_devtype {
>  
>  /**
>   * struct cxl_dpa_perf - DPA performance property entry
> - * @dpa_range - range for DPA address
> - * @coord - QoS performance data (i.e. latency, bandwidth)
> - * @qos_class - QoS Class cookies
> + * @dpa_range: range for DPA address
> + * @coord: QoS performance data (i.e. latency, bandwidth)
> + * @qos_class: QoS Class cookies
>   */
>  struct cxl_dpa_perf {
>  	struct range dpa_range;
> @@ -464,13 +464,14 @@ struct cxl_dev_state {
>   * @active_persistent_bytes: sum of hard + soft persistent
>   * @next_volatile_bytes: volatile capacity change pending device reset
>   * @next_persistent_bytes: persistent capacity change pending device reset
> + * @ram_perf: performance data entry matched to RAM partition
> + * @pmem_perf: performance data entry matched to PMEM partition
>   * @event: event log driver state
>   * @poison: poison driver state info
>   * @security: security driver state info
>   * @fw: firmware upload / activation state
> + * @mbox_wait: RCU wait for mbox send completely
>   * @mbox_send: @dev specific transport for transmitting mailbox commands
> - * @ram_perf: performance data entry matched to RAM partition
> - * @pmem_perf: performance data entry matched to PMEM partition
>   *
>   * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for
>   * details on capacity parameters.
> -- 
> 2.37.3
>