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Just reset them. > This cleans up a conditional in the resume code. > > Signed-off-by: Alex Deucher Acked-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 27 +++++++++----------------- > 1 file changed, 9 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > index 6843c2c3d71f5..b9498697ef41c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > @@ -528,13 +528,12 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) > * > * @adev: amdgpu_device pointer > * @i: instance > - * @restore: used to restore wptr when restart > * > - * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. > + * Set up the gfx DMA ring buffers and enable them. > * Return 0 for success. > */ > > -static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) > +static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i) > { > struct amdgpu_ring *ring; > u32 rb_cntl, ib_cntl; > @@ -562,17 +561,10 @@ static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i, bool > WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); > > /* Initialize the ring buffer's read and write pointers */ > - if (restore) { > - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2)); > - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); > - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); > - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); > - } else { > - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); > - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); > - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); > - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); > - } > + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); > + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); > + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); > + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); > > /* setup the wptr shadow polling */ > wptr_gpu_addr = ring->wptr_gpu_addr; > @@ -599,8 +591,7 @@ static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i, bool > WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); > WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); > > - if (!restore) > - ring->wptr = 0; > + ring->wptr = 0; > > /* before programing wptr to a less value, need set minor_ptr_update first */ > WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); > @@ -698,7 +689,7 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) > int i, r; > > for (i = 0; i < adev->sdma.num_instances; i++) { > - r = sdma_v5_2_gfx_resume_instance(adev, i, false); > + r = sdma_v5_2_gfx_resume_instance(adev, i); > if (r) > return r; > } > @@ -1531,7 +1522,7 @@ static int sdma_v5_2_restore_queue(struct amdgpu_ring *ring) > freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0); > WREG32(sdma_v5_2_get_reg_offset(adev, inst_id, mmSDMA0_FREEZE), freeze); > > - r = sdma_v5_2_gfx_resume_instance(adev, inst_id, true); > + r = sdma_v5_2_gfx_resume_instance(adev, inst_id); > > amdgpu_gfx_rlc_exit_safe_mode(adev, 0); >