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(93-34-91-161.ip49.fastwebnet.it. [93.34.91.161]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431935f744esm14487515e9.34.2024.10.25.04.01.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Oct 2024 04:01:35 -0700 (PDT) Message-ID: <671b7a8f.050a0220.5b160.446a@mx.google.com> X-Google-Original-Message-ID: Date: Fri, 25 Oct 2024 13:01:31 +0200 From: Christian Marangi To: Andrew Lunn Cc: Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Matthias Brugger , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [net-next RFC PATCH v2 3/3] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY References: <20241023161958.12056-1-ansuelsmth@gmail.com> <20241023161958.12056-4-ansuelsmth@gmail.com> <4ad7b2e9-ddf1-4a82-9d60-7afd1856c770@lunn.ch> <67192d40.5d0a0220.33f6c1.23bc@mx.google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <67192d40.5d0a0220.33f6c1.23bc@mx.google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241025_040138_409452_B4107AD7 X-CRM114-Status: GOOD ( 28.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Oct 23, 2024 at 07:07:08PM +0200, Christian Marangi wrote: > On Wed, Oct 23, 2024 at 07:00:22PM +0200, Andrew Lunn wrote: > > > +static int an8855_config_init(struct phy_device *phydev) > > > +{ > > > + struct air_an8855_priv *priv = phydev->priv; > > > + int ret; > > > + > > > + /* Enable HW auto downshift */ > > > + ret = phy_write(phydev, AN8855_PHY_PAGE_CTRL, AN8855_PHY_EXT_PAGE); > > > + if (ret) > > > + return ret; > > > + ret = phy_set_bits(phydev, AN8855_PHY_EXT_REG_14, > > > + AN8855_PHY_EN_DOWN_SHFIT); > > > + if (ret) > > > + return ret; > > > + ret = phy_write(phydev, AN8855_PHY_PAGE_CTRL, AN8855_PHY_NORMAL_PAGE); > > > + if (ret) > > > + return ret; > > > > There are locking issues here, which is why we have the helpers > > phy_select_page() and phy_restore_page(). The air_en8811h.c gets this > > right. > > Ugh didn't think about it... The switch address is shared with the PHY > so yes this is a problem. > > Consider that this page thing comes from my speculation... Not really > use if 1f select page... > From what I observed > 0x0 PHY page > 0x1 this strange EXT > 0x4 acess switch register (every PHY can access the switch) > Just to followup on this... I checked air_en8811h registers again and they match MII access to the switch so yes my speculation is correct. Also extra happy since I now know what those magic values means at least for MII. > > > > Is there anything in common with the en8811h? Does it also support > > downshift? Can its LED code be used here? > > > > For some reason part of the LED are controlled by the switch and some > are by the PHY. I still have to investigate that (not giving priority to > it... just on my todo) > > For downshift as you notice it's a single bit with no count... > From their comments in the original driver it's said "Enable HW > autodownshift" > > Trying to reach them but currently it's all very obscure. > > -- > Ansuel -- Ansuel