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(93-34-91-161.ip49.fastwebnet.it. [93.34.91.161]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3861f4a8591sm2443049f8f.36.2024.12.05.09.17.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Dec 2024 09:17:23 -0800 (PST) Message-ID: <6751e023.5d0a0220.394b90.7bc9@mx.google.com> X-Google-Original-Message-ID: Date: Thu, 5 Dec 2024 18:17:18 +0100 From: Christian Marangi To: Vladimir Oltean Cc: Andrew Lunn , Florian Fainelli , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Matthias Brugger , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@airoha.com Subject: Re: [net-next PATCH v9 3/4] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver References: <20241205145142.29278-1-ansuelsmth@gmail.com> <20241205145142.29278-4-ansuelsmth@gmail.com> <20241205162759.pm3iz42bhdsvukfm@skbuf> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241205162759.pm3iz42bhdsvukfm@skbuf> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241205_091726_117893_55C4E804 X-CRM114-Status: GOOD ( 26.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Dec 05, 2024 at 06:27:59PM +0200, Vladimir Oltean wrote: > On Thu, Dec 05, 2024 at 03:51:33PM +0100, Christian Marangi wrote: > > +static int an8855_efuse_read(void *context, unsigned int offset, > > + void *val, size_t bytes) > > +{ > > + struct an8855_priv *priv = context; > > + > > + return regmap_bulk_read(priv->regmap, AN8855_EFUSE_DATA0 + offset, > > + val, bytes / sizeof(u32)); > > +} > > + > > +static struct nvmem_config an8855_nvmem_config = { > > + .name = "an8855-efuse", > > + .size = AN8855_EFUSE_CELL * sizeof(u32), > > + .stride = sizeof(u32), > > + .word_size = sizeof(u32), > > + .reg_read = an8855_efuse_read, > > +}; > > + > > +static int an8855_sw_register_nvmem(struct an8855_priv *priv) > > +{ > > + struct nvmem_device *nvmem; > > + > > + an8855_nvmem_config.priv = priv; > > + an8855_nvmem_config.dev = priv->dev; > > + nvmem = devm_nvmem_register(priv->dev, &an8855_nvmem_config); > > + if (IS_ERR(nvmem)) > > + return PTR_ERR(nvmem); > > + > > + return 0; > > +} > > At some point we should enforce the rule that new drivers for switch > SoCs with complex peripherals should use MFD and move all non-networking > peripherals to drivers handled by their respective subsystems. > > I don't have the expertise to review a nvmem driver, and the majority of > them are in drivers/nvmem, with a dedicated subsystem and maintainer. > In general I want to make sure it is clear that I don't encourage the > model where DSA owns the entire mdio_device. > > What other peripherals are there on this SoC other than an MDIO bus and > an EFUSE? IRQCHIP, GPIOs, LED controller, sensors? > > You can take a look at drivers/mfd/ocelot* and > Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml for an example on > how to use mfd for the top-level MDIO device, and DSA as just the driver > for the Ethernet switch component (which will be represented as a > platform_device). Hi Vladimir, I checked the examples and one problems that comes to me is how to model this if only MDIO is used as a comunication method. Ocelot have PCIE or SPI but this switch only comunicate with MDIO on his address. So where should I place the SoC or MFD node? In the switch root node? Also the big problem is how to model accessing the register with MDIO with an MFD implementation. Anyway just to make sure the Switch SoC doesn't expose an actualy MDIO bus, that is just to solve the problem with the Switch Address shared with one of the port. (Switch Address can be accessed by every switch port with a specific page set) But yes the problem is there... Function is not implemented but the switch have i2c interface, minimal CPU, GPIO and Timer in it. Happy to make the required changes, just very confused on how the final DT node structure. -- Ansuel