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(93-34-91-161.ip49.fastwebnet.it. [93.34.91.161]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434da0da461sm33743535e9.20.2024.12.05.11.36.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Dec 2024 11:36:35 -0800 (PST) Message-ID: <675200c3.7b0a0220.236ac3.9edf@mx.google.com> X-Google-Original-Message-ID: Date: Thu, 5 Dec 2024 20:36:30 +0100 From: Christian Marangi To: Vladimir Oltean Cc: Andrew Lunn , Florian Fainelli , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Matthias Brugger , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@airoha.com Subject: Re: [net-next PATCH v9 3/4] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver References: <20241205145142.29278-4-ansuelsmth@gmail.com> <20241205162759.pm3iz42bhdsvukfm@skbuf> <20241205145142.29278-1-ansuelsmth@gmail.com> <20241205145142.29278-4-ansuelsmth@gmail.com> <20241205162759.pm3iz42bhdsvukfm@skbuf> <6751e023.5d0a0220.394b90.7bc9@mx.google.com> <6751e023.5d0a0220.394b90.7bc9@mx.google.com> <20241205180539.6t5iz2m3wjjwyxp3@skbuf> <6751f125.5d0a0220.255b79.7be0@mx.google.com> <20241205185037.g6cqejgad5jamj7r@skbuf> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241205185037.g6cqejgad5jamj7r@skbuf> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241205_113637_573086_E324D588 X-CRM114-Status: GOOD ( 32.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Dec 05, 2024 at 08:50:37PM +0200, Vladimir Oltean wrote: > On Thu, Dec 05, 2024 at 07:29:53PM +0100, Christian Marangi wrote: > > Ohhhh ok, wasn't clear to me the MFD driver had to be placed in the mdio > > node. > > > > To make it clear this would be an implementation. > > > > mdio_bus: mdio-bus { > > #address-cells = <1>; > > #size-cells = <0>; > > > > ... > > > > mfd@1 { > > compatible = "airoha,an8855-mfd"; > > reg = <1>; > > > > nvmem_node { > > ... > > }; > > > > switch_node { > > ... > > }; > > }; > > }; > > I mean, I did mention Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml > in my initial reply, which has an example with exactly this layout... > > > The difficulties I found (and maybe is very easy to solve and I'm > > missing something here) is that switch and internal PHY port have the > > same address and conflicts. > > > > Switch will be at address 1 (or 2 3 4 5... every port can access switch > > register with page 0x4) > > > > DSA port 0 will be at address 1, that is already occupied by the switch. > > > > Defining the DSA port node on the host MDIO bus works correctly for > > every port but for port 0 (the one at address 1), the kernel complains > > and is not init. (as it does conflict with the switch that is at the > > same address) (can't remember the exact warning) > > Can any of these MDIO addresses (switch or ports) be changed through registers? No, it can only be changed the BASE address that change the address of each port. port 0 is base address port 1 is base address + 1 port 2 is base address + 2... > > I guess the non-hack solution would be to permit MDIO buses to have > #size-cells = 1, and MDIO devices to acquire a range of the address > space, rather than just one address. Though take this with a grain of > salt, I have a lot more to learn. I remember this was an idea when PHY Package API were proposed and was rejected as we wanted PHY to be single reg. > > If neither of those are options, in principle the hack with just > selecting, randomly, one of the N internal PHY addresses as the central > MDIO address should work equally fine regardless of whether we are > talking about the DSA switch's MDIO address here, or the MFD device's > MDIO address. > > With MFD you still have the option of creating a fake MDIO controller > child device, which has mdio-parent-bus = <&host_bus>, and redirecting > all user port phy-handles to children of this bus. Since all regmap I/O > of this fake MDIO bus goes to the MFD driver, you can implement there > your hacks with page switching etc etc, and it should be equally > safe. I wonder if a node like this would be more consistent and descriptive? mdio_bus: mdio-bus { #address-cells = <1>; #size-cells = <0>; ... mfd@1 { compatible = "airoha,an8855-mfd"; reg = <1>; nvmem_node { ... }; switch_node { ports { port@0 { phy-handle = <&phy>; }; port@1 { phy-handle = <&phy_2>; } }; }; phy: phy_node { }; }; phy_2: phy@2 { reg = <2>; } phy@3 { reg = <3>; } .. }; No idea how to register that single phy in mfd... I guess a fake mdio is needed anyway... What do you think of this node example? Or not worth it and better have the fake MDIO with all the switch PHY in it? -- Ansuel