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(93-34-91-161.ip49.fastwebnet.it. [93.34.91.161]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434fb066874sm69945475e9.32.2024.12.10.12.56.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Dec 2024 12:56:33 -0800 (PST) Message-ID: <6758ab01.7b0a0220.b8716.380c@mx.google.com> X-Google-Original-Message-ID: Date: Tue, 10 Dec 2024 21:56:30 +0100 From: Christian Marangi To: Vladimir Oltean Cc: Andrew Lunn , Florian Fainelli , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , Matthias Brugger , AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@airoha.com Subject: Re: [net-next PATCH v9 3/4] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver References: <20241205162759.pm3iz42bhdsvukfm@skbuf> <6751e023.5d0a0220.394b90.7bc9@mx.google.com> <6751e023.5d0a0220.394b90.7bc9@mx.google.com> <20241205180539.6t5iz2m3wjjwyxp3@skbuf> <6751f125.5d0a0220.255b79.7be0@mx.google.com> <20241205185037.g6cqejgad5jamj7r@skbuf> <675200c3.7b0a0220.236ac3.9edf@mx.google.com> <20241205235709.pa5shi7mh26cnjhn@skbuf> <67543b6f.df0a0220.3bd32.6d5d@mx.google.com> <20241210203148.2lw5zwldazmwr2rn@skbuf> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241210203148.2lw5zwldazmwr2rn@skbuf> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241210_125636_159397_63F8DC55 X-CRM114-Status: GOOD ( 18.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Dec 10, 2024 at 10:31:48PM +0200, Vladimir Oltean wrote: > On Sat, Dec 07, 2024 at 01:11:23PM +0100, Christian Marangi wrote: > > I finished testing and this works, I'm not using mdio-parent-bus tho as > > the mdio-mux driver seems overkill for the task and problematic for PAGE > > handling. (mdio-mux doesn't provide a way to give the current addr that > > is being accessed) > > The use of mdio-parent-bus doesn't necessarily imply an mdio-mux. For > example, you'll also see it used in net/dsa/microchip,ksz.yaml. > > You say this switch is also accessible over I2C. How are the internal > PHYs accessed in that case? Still over MDIO? If so, it would be nice to > have a unified scheme for both I2C-controlled switch and MDIO-controlled > switch, which is something that mdio-parent-bus would permit. What is not clear to me is where that property should be used in the code or it's just for reference in DT to describe what is the parent? Given MFD implementation, I pass the bus by accessing the MFD priv struct so having the parent property is redundant. -- Ansuel