Re: [GIT PULL] EDAC pile for 5.4 -> AMD family 17h, model 70h support

["Ghannam, Yazen" <Yazen.Ghannam@amd.com>]

On 10/8/2019 7:50 AM, Borislav Petkov wrote:
> On Mon, Oct 07, 2019 at 08:58:30AM -0400, Jeff God wrote:
>> I want to test that the ECC reporting is working on my machine (so
>> that when real errors will happen one day I will get notified)
>>
>> The method I described previously to generate errors by overclocking
>> memory was my initial method to generate real errors, which proved to
>> work well on another system with a previous generation AMD Ryzen 2700x
>> and similar motherboard and same memory, but on this system it does
>> not report any error, although turning off ECC in the bios showed that
>> memory corruption is happening fairly quickly in this case, hence the
>> conclusion that error reporting was probably not working but the
>> underlying memory error correction system may be working.
> 
> Yeah, if I inject an "sw" type here, I get immediately:
> 
> [  264.740840] [Hardware Error]: Corrected error, no action required.
> [  264.740942] [Hardware Error]: CPU:2 (17:1:2) MC4_STATUS[-|CE|MiscV|AddrV|-|SyndV|CECC|-|-|Scrub]: 0x9c7d410092080813
> [  264.741074] [Hardware Error]: Error Addr: 0x000000006d3d483b
> [  264.741169] [Hardware Error]: IPID: 0x0000000000000000, Syndrome: 0x0000000000000000
> [  264.741279] [Hardware Error]: Bank 4 is reserved.
> [  264.741368] [Hardware Error]: cache level: L3/GEN, mem/io: MEM, mem-tx: RD, part-proc: SRC (no timeout)
> 
> but doing a hw injection seems to do all that it should do:
> 
> [  245.658175] mce: do_inject: CPIU2, toggling...
> [  245.658375] mce: prepare_msrs
> [  245.658507] mce: trigger_mce: CPU2
> 
> but nothing happens.
> 
> Yazen, are we missing something here?
> 
> See upthread for details - thread is on linux-edac@.
> 

Hi guys,
The "hw" option requires a non-zero, valid MCA_STATUS to be used so that the
MCA handlers will find the error in the hardware and report it.

Jean-Frederic,
You originally had status=0 which explains why nothing was reported.

Boris,
You used non-zero values, but you targetted bank 4. This bank is
Read-as-Zero/Writes-Ignored on Family 17h and later. So even though you used
good values, the MCA handlers won't find anything because bank 4 is RAZ.


Here are some values I took from a real corrected DRAM ECC error.

status=0x9c2041000000011b
synd=0x7c7600010a800100

The memory controller banks are 17 (channel 0) and 18 (channel 1) on Family
17h Model 7Xh, and these are managed by CPU 0.

Please give these values a try and let me know how it goes.

Thanks,
Yazen