From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tomasz Figa Subject: Re: [PATCH 1/2] clk: samsung: Add GPLL freq table for exynos5250 SoC Date: Wed, 28 Aug 2013 10:06:49 +0200 Message-ID: <6793396.xvnsuP0Ggu@flatron> References: <1376301734-21847-1-git-send-email-vikas.sajjan@linaro.org> <1376301734-21847-2-git-send-email-vikas.sajjan@linaro.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Return-path: Received: from mail-ea0-f178.google.com ([209.85.215.178]:60737 "EHLO mail-ea0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752345Ab3H1IGw (ORCPT ); Wed, 28 Aug 2013 04:06:52 -0400 Received: by mail-ea0-f178.google.com with SMTP id a15so2766500eae.37 for ; Wed, 28 Aug 2013 01:06:51 -0700 (PDT) In-Reply-To: <1376301734-21847-2-git-send-email-vikas.sajjan@linaro.org> Sender: linux-samsung-soc-owner@vger.kernel.org List-Id: linux-samsung-soc@vger.kernel.org To: Vikas Sajjan Cc: mturquette@linaro.org, linux-samsung-soc@vger.kernel.org, kgene.kim@samsung.com, t.figa@samsung.com, dianders@chromium.org, patches@linaro.org, linaro-kernel@lists.linaro.org Hi Vikas, On Monday 12 of August 2013 15:32:13 Vikas Sajjan wrote: > Adds GPLL freq table for exynos5250 SoC. > > Signed-off-by: Vikas Sajjan > --- > drivers/clk/samsung/clk-exynos5250.c | 19 ++++++++++++++++++- > 1 file changed, 18 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-exynos5250.c > b/drivers/clk/samsung/clk-exynos5250.c index a9916a4..c400e82 100644 > --- a/drivers/clk/samsung/clk-exynos5250.c > +++ b/drivers/clk/samsung/clk-exynos5250.c > @@ -494,6 +494,21 @@ static struct samsung_gate_clock > exynos5250_gate_clks[] __initdata = { GATE(g2d, "g2d", "aclk200", > GATE_IP_ACP, 3, 0, 0), > }; > > +static struct samsung_pll_rate_table gpll_24mhz_tbl[] __initdata = { > + /* sorted in descending order */ > + /* PLL_35XX_RATE(rate, m, p, s) */ > + PLL_35XX_RATE(1400000000, 175, 3, 0), /* for 466MHz */ > + PLL_35XX_RATE(800000000, 100, 3, 0), /* for 400MHz, 200MHz */ > + PLL_35XX_RATE(667000000, 389, 7, 1), /* for 333MHz, 222MHz, 166MHz */ Frequency generated by this entry is not exactly 667 MHz, but rather 666857142 Hz. This must be reflected by the rate field or PLL rate setting won't work correctly otherwise. > + PLL_35XX_RATE(600000000, 200, 4, 1), /* for 300MHz, 200MHz, 150MHz > */ + PLL_35XX_RATE(533000000, 533, 12, 1), /* for 533MHz, 266MHz, > 133MHz */ + PLL_35XX_RATE(450000000, 450, 12, 1), /* for 450Hz */ > + PLL_35XX_RATE(400000000, 100, 3, 1), > + PLL_35XX_RATE(333000000, 222, 4, 2), > + PLL_35XX_RATE(200000000, 100, 3, 2), > + { }, > +}; > + > static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { > /* sorted in descending order */ > /* PLL_36XX_RATE(rate, m, p, s, k) */ > @@ -565,8 +580,10 @@ static void __init exynos5250_clk_init(struct > device_node *np) > > fin_pll_rate = _get_rate("fin_pll"); > > - if (fin_pll_rate == 24 * MHZ) > + if (fin_pll_rate == 24 * MHZ) { > exynos5250_plls[epll].rate_table = epll_24mhz_tbl; > + exynos5250_plls[gpll].rate_table = gpll_24mhz_tbl; > + } Also you could rebase this series on my patches[1] cleaning several things up, to simplify this table setting code a bit. [1] - http://www.spinics.net/lists/arm-kernel/msg269848.html Best regards, Tomasz