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[88.21.202.78]) by smtp.gmail.com with ESMTPSA id v15sm8671191wrf.7.2020.02.11.22.33.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Feb 2020 22:33:22 -0800 (PST) Subject: Re: [PATCH] target/arm: Implement ARMv8.1-VMID16 extension To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20200210120146.17631-1-peter.maydell@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <679ea0df-0aed-6268-9b28-b377ba51a1dc@redhat.com> Date: Wed, 12 Feb 2020 07:33:21 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200210120146.17631-1-peter.maydell@linaro.org> Content-Language: en-US X-MC-Unique: JmH3ho9AMmu7KiuajI55og-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.61 X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: "Qemu-arm" X-TUID: F+monPs0lMN3 On 2/10/20 1:01 PM, Peter Maydell wrote: > The ARMv8.1-VMID16 extension extends the VMID from 8 bits to 16 bits: >=20 > * the ID_AA64MMFR1_EL1.VMIDBits field specifies whether the VMID is > 8 or 16 bits > * the VMID field in VTTBR_EL2 is extended to 16 bits > * VTCR_EL2.VS lets the guest specify whether to use the full 16 bits, > or use the backwards-compatible 8 bits >=20 > For QEMU implementing this is trivial: > * we do not track VMIDs in TLB entries, so we never use the VMID field > * we treat any write to VTTBR_EL2, not just a change to the VMID field > bits, as a "possible VMID change" that causes us to throw away TLB > entries, so that code doesn't need changing > * we allow the guest to read/write the VTCR_EL2.VS bit already >=20 > So all that's missing is the ID register part: report that we support > VMID16 in our 'max' CPU. >=20 > Signed-off-by: Peter Maydell > --- > Not something anybody's been asking for, but worthwhile as > a step towards finishing off support for all the v8.1 extensions. >=20 > target/arm/cpu64.c | 1 + > 1 file changed, 1 insertion(+) >=20 > diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c > index 2d97bf45e1e..bf2cf278c03 100644 > --- a/target/arm/cpu64.c > +++ b/target/arm/cpu64.c > @@ -672,6 +672,7 @@ static void aarch64_max_initfn(Object *obj) > t =3D cpu->isar.id_aa64mmfr1; > t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ > t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); > + t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ > cpu->isar.id_aa64mmfr1 =3D t; > =20 > /* Replicate the same data to the 32-bit id registers. */ >=20 Trivial conflict with: commit cd3f80aba0c559a6291f7c3e686422b15381f6b7 Author: Richard Henderson Date: Fri Feb 7 14:04:27 2020 +0000 target/arm: Enable ARMv8.1-VHE in -cpu max Tested-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200206105448.4726-38-richard.henderson@linaro.org Signed-off-by: Peter Maydell diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2d97bf45e1..c80fb5fd43 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -672,6 +672,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64mmfr1; t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); cpu->isar.id_aa64mmfr1 =3D t; /* Replicate the same data to the 32-bit id registers. */