From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: frank.chang@sifive.com, qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>, Weiwei Li <liwei1518@gmail.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
"open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
Jerry Zhang Jian <jerry.zhangjian@sifive.com>,
Max Chou <max.chou@sifive.com>
Subject: Re: [PATCH v2 5/6] target/riscv: Add Zc extension implied rule
Date: Thu, 20 Jun 2024 16:53:50 -0300 [thread overview]
Message-ID: <67d320fe-66ff-4686-8ea6-cf68190f9132@ventanamicro.com> (raw)
In-Reply-To: <20240616024657.17948-6-frank.chang@sifive.com>
On 6/15/24 11:46 PM, frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Zc extension has special implied rules that need to be handled separately.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
> Tested-by: Max Chou <max.chou@sifive.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/tcg/tcg-cpu.c | 34 ++++++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index f8d6371764..fe84d4402e 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -902,11 +902,45 @@ static void cpu_enable_implied_rule(RISCVCPU *cpu,
> }
> }
>
> +/* Zc extension has special implied rules that need to be handled separately. */
> +static void cpu_enable_zc_implied_rules(RISCVCPU *cpu)
> +{
> + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
> + CPURISCVState *env = &cpu->env;
> +
> + if (cpu->cfg.ext_zce) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
> +
> + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
> + }
> + }
> +
> + /* Zca, Zcd and Zcf has a PRIV 1.12.0 restriction */
> + if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
> +
> + if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
> + }
> +
> + if (riscv_has_ext(env, RVD)) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true);
> + }
> + }
> +}
> +
> static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu)
> {
> RISCVCPUImpliedExtsRule *rule;
> int i;
>
> + /* Enable the implied extensions for Zc. */
> + cpu_enable_zc_implied_rules(cpu);
> +
> /* Enable the implied MISAs. */
> for (i = 0; (rule = riscv_misa_implied_rules[i]); i++) {
> if (riscv_has_ext(&cpu->env, rule->ext)) {
next prev parent reply other threads:[~2024-06-20 19:54 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-16 2:46 [PATCH v2 0/6] Introduce extension implied rules frank.chang
2024-06-16 2:46 ` [PATCH v2 1/6] target/riscv: Introduce extension implied rules definition frank.chang
2024-06-20 19:51 ` Daniel Henrique Barboza
2024-06-16 2:46 ` [PATCH v2 2/6] target/riscv: Introduce extension implied rule helpers frank.chang
2024-06-20 19:52 ` Daniel Henrique Barboza
2024-06-21 4:14 ` Alistair Francis
2024-06-21 6:50 ` Frank Chang
2024-06-16 2:46 ` [PATCH v2 3/6] target/riscv: Add MISA implied rules frank.chang
2024-06-20 19:53 ` Daniel Henrique Barboza
2024-06-16 2:46 ` [PATCH v2 4/6] target/riscv: Add standard extension " frank.chang
2024-06-20 19:53 ` Daniel Henrique Barboza
2024-06-16 2:46 ` [PATCH v2 5/6] target/riscv: Add Zc extension implied rule frank.chang
2024-06-20 19:53 ` Daniel Henrique Barboza [this message]
2024-06-16 2:46 ` [PATCH v2 6/6] target/riscv: Remove extension auto-update check statements frank.chang
2024-06-20 19:54 ` Daniel Henrique Barboza
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