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Fri, 26 Sep 2025 03:52:59 -0700 (PDT) Message-ID: <67dd3659-916b-4e64-afe2-e13fdc8d31f0@suse.com> Date: Fri, 26 Sep 2025 12:52:58 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [XEN][PATCH] x86/hvm: vlapic: fix RO bits emulation in LVTx regs To: Grygorii Strashko Cc: Andrew Cooper , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Alejandro Vallejo , Jason Andryuk , "xen-devel@lists.xenproject.org" References: <20250925195558.519568-1-grygorii_strashko@epam.com> Content-Language: en-US From: Jan Beulich Autocrypt: addr=jbeulich@suse.com; keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 26.09.2025 12:38, Grygorii Strashko wrote: > On 26.09.25 11:17, Jan Beulich wrote: >> On 25.09.2025 21:55, Grygorii Strashko wrote: >>> From: Grygorii Strashko >>> >>> The LAPIC LVTx registers have two RO bits: >>> - all: Delivery Status (DS) bit 12 >>> - LINT0/LINT1: Remote IRR Flag (RIR) bit 14. >>> This bit is reserved for other LVTx regs with RAZ/WI access type (MMIO), while >>> WRMSR (guest_wrmsr_x2apic()) has appropiate checks for reserved bits >>> (MBZ access type). >> >> Question is what the behavior is for writing the r/o (but not reserved) bits. >> I wasn't able to find any statement in the SDM. > > Me too. Usually RO/WI on most HW. > For example, LAPIC MMIO "Write" will be ignored (WRMSR will trigger exception). My remark was specifically about WRMSR, and what you say here contradicts ... >>> --- a/xen/arch/x86/hvm/vlapic.c >>> +++ b/xen/arch/x86/hvm/vlapic.c >>> @@ -880,6 +880,7 @@ void vlapic_reg_write(struct vcpu *v, unsigned int reg, uint32_t val) >>> if ( vlapic_sw_disabled(vlapic) ) >>> val |= APIC_LVT_MASKED; >>> val &= array_access_nospec(vlapic_lvt_mask, (reg - APIC_LVTT) >> 4); >>> + val &= ~(APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING); >> >> There shouldn't be a 2nd &= here; what needs adding should imo be added to >> (really: removed from) vlapic_lvt_mask[]. > > I'll try it. > > (Orthogonal to this I wonder whether >> guest_wrmsr_x2apic() wouldn't better use that array, too.) > > WRMSR checks for MBZ. RO bits are not MBZ, so masks are different. ... what you say here. >> While looking at this, don't we have an issue with CMCI as well? > > I see no APIC_CMCI write emulation. only read. guest_wrmsr_x2apic() has case APIC_CMCI: >> guest_{rd,wr}msr_x2apic() handle it, but vlapic_reg_write() doesn't. I.e. on >> AMD we would fail to deliver #GP when the guest accesses it, while on Intel >> we would lose the value written. And we also don't set its mask bit in >> vlapic_do_init(). I guess I need to make a patch ... > > Is'n it depends on CMCI capability exposing to guest? Yes, that's part of what I was (effectively) saying. > (have no idea what's CMCI :) Corrected Machine Check Interrupt. Jan