From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38534C2BA2B for ; Fri, 10 Apr 2020 14:18:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0E67820CC7 for ; Fri, 10 Apr 2020 14:18:57 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PzrJ1G+g" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726670AbgDJOS4 (ORCPT ); Fri, 10 Apr 2020 10:18:56 -0400 Received: from mail-lj1-f193.google.com ([209.85.208.193]:36322 "EHLO mail-lj1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726145AbgDJOS4 (ORCPT ); Fri, 10 Apr 2020 10:18:56 -0400 Received: by mail-lj1-f193.google.com with SMTP id n23so2108551ljg.3; Fri, 10 Apr 2020 07:18:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=csrvl1c+O62QiY1i5I2vPcapPdMbP20Dc619rzOjrHg=; b=PzrJ1G+gJpRmx0ywjb/789Cgg1GrSezUTE0/LfFzYMCsmYLNAHM3H+oGpUNICrgdXZ aXDTfyc0dgSMHiUT0s17XtuLyqQ06SYP5mE6aS8fnmTyIBM60Bg/jOLf7F6dna5NMsMR 8n0Day9czPDgppvmia1qnyEtX0wPI2TIOWRzxq3STR0XS15woWHGVFLhBq8allCjGoKF ZQIpbIK2AkLA8IK/svBpH3HlGRA0XqhT0UrWCMZJD5OKCi+gJxXFaWst4tqCQZ86tJC6 6Zzd/T/yvHS7hdvhNJUTqfZCPnRjhSDuBJ7RgbYfIIkJEGXucntlRS+tR6tOQ0y6+xdF kASA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=csrvl1c+O62QiY1i5I2vPcapPdMbP20Dc619rzOjrHg=; b=djxDj9ouNA66rpMIvy9BtioKuQq42ZNOk25S/beRG4dYXE5cQAhshYWZvmxX0xk2Fm 6xgF2fvaUFmYCNhHitEo7mJ2cDrNgP3UlgcRAhme/NmfBf5wCx8E0/Zytx87TC23eUmp UNd4d0rh1zEhnZqM5uTMKNlqiW2KI6UoLNSBuqsfCeglXpUwtjGqb09NY36cy4uT8lWn lex2DqaM1RqshSCKmRsJUEXqZF7Iuqn5DpcH8vDGFxQifIUwazVik7SpmohTCjpVYREg I4m9OhU8MObG1zUyLgmsfCHUUb3FLwVftLllKEy4axigNr8c9fXy35aWGBSCR/OOULJk v1Yw== X-Gm-Message-State: AGi0PubEXeBXcu6ZoJc+rju8FzNlBCletfU+kuWpMZX8SYK5MZggiuN8 aLdPQnr2aztk2wMprdNarSY= X-Google-Smtp-Source: APiQypL8wSZ3+zuj3JdwrMxl2nUdiO7+MYxW0LLqG0DA915dib8zv1EuWcyyuRt5PD81k/AxqIRe1g== X-Received: by 2002:a2e:b80d:: with SMTP id u13mr3126155ljo.166.1586528333328; Fri, 10 Apr 2020 07:18:53 -0700 (PDT) Received: from [192.168.2.145] (ppp91-78-208-152.pppoe.mtu-net.ru. [91.78.208.152]) by smtp.googlemail.com with ESMTPSA id u1sm1129675ljo.65.2020.04.10.07.18.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Apr 2020 07:18:52 -0700 (PDT) Subject: Re: [PATCH v6 10/14] memory: tegra: Add EMC scaling sequence code for Tegra210 To: Thierry Reding , Rob Herring Cc: Jon Hunter , Michael Turquette , Stephen Boyd , Joseph Lo , linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <20200409175238.3586487-1-thierry.reding@gmail.com> <20200409175238.3586487-11-thierry.reding@gmail.com> From: Dmitry Osipenko Message-ID: <682c661d-ea3a-7b9a-42f0-d5473b969aa2@gmail.com> Date: Fri, 10 Apr 2020 17:18:51 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200409175238.3586487-11-thierry.reding@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org 09.04.2020 20:52, Thierry Reding пишет: ... > +static void tegra210_emc_r21021_set_clock(struct tegra210_emc *emc, u32 clksrc) > +{ > + /* > + * This is the timing table for the source frequency. It does _not_ > + * necessarily correspond to the actual timing values in the EMC at the > + * moment. If the boot BCT differs from the table then this can happen. > + * However, we need it for accessing the dram_timings (which are not > + * really registers) array for the current frequency. > + */ > + u32 tmp, cya_allow_ref_cc = 0, ref_b4_sref_en = 0, cya_issue_pc_ref = 0; > + struct tegra210_emc_timing *fake, *last = emc->last, *next = emc->next; > + u32 bg_regulator_switch_complete_wait_clks, bg_regulator_mode_change; > + u32 opt_zcal_en_cc, opt_do_sw_qrst = 1, opt_dvfs_mode, opt_dll_mode; > + u32 emc_zcal_wait_cnt_old, emc_zcal_wait_cnt_new, emc_dbg_active; > + u32 opt_cc_short_zcal = 1, opt_short_zcal = 1, opt_war_200024907; > + u32 tRTM, RP_war, R2P_war, TRPab_war, deltaTWATM, W2P_war, tRPST; > + u32 adel = 0, compensate_trimmer_applicable = 0, mrw_req, value; > + unsigned long next_timing_rate_mhz = next->rate / 1000, delay; > + u32 tZQCAL_lpddr4 = 1000000, zq_wait_long, shared_zq_resistor; > + s32 zq_latch_dvfs_wait_time, tZQCAL_lpddr4_fc_adj, nRTP; > + u32 tFC_lpddr4 = 1000 * next->dram_timings[T_FC_LPDDR4]; > + u32 emc_auto_cal_config, auto_cal_en, mr13_catr_enable; > + u32 zq_op, zcal_wait_time_clocks, zcal_wait_time_ps; > + u32 emc_cfg, emc_sel_dpd_ctrl, emc_zcal_interval; > + int next_push, next_dq_e_ivref, next_dqs_e_ivref; > + u32 mr13_flip_fspwr, mr13_flip_fspop, is_lpddr3; > + u32 enable_bglp_regulator, enable_bg_regulator; > + u32 emc_dbg_o, emc_cfg_pipe_clk_o, emc_pin_o; > + u32 ramp_up_wait = 0, ramp_down_wait = 0; > + u32 save_restore_clkstop_pd = 1, dll_out; > + u32 ref_delay_mult, ref_delay, dram_type; > + static u32 fsp_for_next_freq; > + /* In picoseconds. */ > + u32 source_clock_period, destination_clock_period; > + u32 zqcal_before_cc_cutoff = 2400; > + unsigned int i; What about to try to replace this massive egyptian construction with a single "u32 val;" ? ... > + emc_readl(emc, EMC_CFG); > + emc_auto_cal_config = emc_readl(emc, EMC_AUTO_CAL_CONFIG); And remove all the "dummy" variable assigns in the code? ... > emc_auto_cal_config = next->emc_auto_cal_config; ...> + emc_zcal_interval = 0; And replace all "constant" variables with a raw value in place in the code? From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dmitry Osipenko Subject: Re: [PATCH v6 10/14] memory: tegra: Add EMC scaling sequence code for Tegra210 Date: Fri, 10 Apr 2020 17:18:51 +0300 Message-ID: <682c661d-ea3a-7b9a-42f0-d5473b969aa2@gmail.com> References: <20200409175238.3586487-1-thierry.reding@gmail.com> <20200409175238.3586487-11-thierry.reding@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20200409175238.3586487-11-thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> Content-Language: en-US Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Thierry Reding , Rob Herring Cc: Jon Hunter , Michael Turquette , Stephen Boyd , Joseph Lo , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org List-Id: linux-tegra@vger.kernel.org 09.04.2020 20:52, Thierry Reding пишет: ... > +static void tegra210_emc_r21021_set_clock(struct tegra210_emc *emc, u32 clksrc) > +{ > + /* > + * This is the timing table for the source frequency. It does _not_ > + * necessarily correspond to the actual timing values in the EMC at the > + * moment. If the boot BCT differs from the table then this can happen. > + * However, we need it for accessing the dram_timings (which are not > + * really registers) array for the current frequency. > + */ > + u32 tmp, cya_allow_ref_cc = 0, ref_b4_sref_en = 0, cya_issue_pc_ref = 0; > + struct tegra210_emc_timing *fake, *last = emc->last, *next = emc->next; > + u32 bg_regulator_switch_complete_wait_clks, bg_regulator_mode_change; > + u32 opt_zcal_en_cc, opt_do_sw_qrst = 1, opt_dvfs_mode, opt_dll_mode; > + u32 emc_zcal_wait_cnt_old, emc_zcal_wait_cnt_new, emc_dbg_active; > + u32 opt_cc_short_zcal = 1, opt_short_zcal = 1, opt_war_200024907; > + u32 tRTM, RP_war, R2P_war, TRPab_war, deltaTWATM, W2P_war, tRPST; > + u32 adel = 0, compensate_trimmer_applicable = 0, mrw_req, value; > + unsigned long next_timing_rate_mhz = next->rate / 1000, delay; > + u32 tZQCAL_lpddr4 = 1000000, zq_wait_long, shared_zq_resistor; > + s32 zq_latch_dvfs_wait_time, tZQCAL_lpddr4_fc_adj, nRTP; > + u32 tFC_lpddr4 = 1000 * next->dram_timings[T_FC_LPDDR4]; > + u32 emc_auto_cal_config, auto_cal_en, mr13_catr_enable; > + u32 zq_op, zcal_wait_time_clocks, zcal_wait_time_ps; > + u32 emc_cfg, emc_sel_dpd_ctrl, emc_zcal_interval; > + int next_push, next_dq_e_ivref, next_dqs_e_ivref; > + u32 mr13_flip_fspwr, mr13_flip_fspop, is_lpddr3; > + u32 enable_bglp_regulator, enable_bg_regulator; > + u32 emc_dbg_o, emc_cfg_pipe_clk_o, emc_pin_o; > + u32 ramp_up_wait = 0, ramp_down_wait = 0; > + u32 save_restore_clkstop_pd = 1, dll_out; > + u32 ref_delay_mult, ref_delay, dram_type; > + static u32 fsp_for_next_freq; > + /* In picoseconds. */ > + u32 source_clock_period, destination_clock_period; > + u32 zqcal_before_cc_cutoff = 2400; > + unsigned int i; What about to try to replace this massive egyptian construction with a single "u32 val;" ? ... > + emc_readl(emc, EMC_CFG); > + emc_auto_cal_config = emc_readl(emc, EMC_AUTO_CAL_CONFIG); And remove all the "dummy" variable assigns in the code? ... > emc_auto_cal_config = next->emc_auto_cal_config; ...> + emc_zcal_interval = 0; And replace all "constant" variables with a raw value in place in the code? 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[91.78.208.152]) by smtp.googlemail.com with ESMTPSA id u1sm1129675ljo.65.2020.04.10.07.18.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Apr 2020 07:18:52 -0700 (PDT) Subject: Re: [PATCH v6 10/14] memory: tegra: Add EMC scaling sequence code for Tegra210 To: Thierry Reding , Rob Herring References: <20200409175238.3586487-1-thierry.reding@gmail.com> <20200409175238.3586487-11-thierry.reding@gmail.com> From: Dmitry Osipenko Message-ID: <682c661d-ea3a-7b9a-42f0-d5473b969aa2@gmail.com> Date: Fri, 10 Apr 2020 17:18:51 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.5.0 MIME-Version: 1.0 In-Reply-To: <20200409175238.3586487-11-thierry.reding@gmail.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200410_071857_300826_CBB9D76F X-CRM114-Status: GOOD ( 15.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Stephen Boyd , Michael Turquette , Jon Hunter , Joseph Lo , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org MDkuMDQuMjAyMCAyMDo1MiwgVGhpZXJyeSBSZWRpbmcg0L/QuNGI0LXRgjoKLi4uCj4gK3N0YXRp YyB2b2lkIHRlZ3JhMjEwX2VtY19yMjEwMjFfc2V0X2Nsb2NrKHN0cnVjdCB0ZWdyYTIxMF9lbWMg KmVtYywgdTMyIGNsa3NyYykKPiArewo+ICsJLyoKPiArCSAqIFRoaXMgaXMgdGhlIHRpbWluZyB0 YWJsZSBmb3IgdGhlIHNvdXJjZSBmcmVxdWVuY3kuIEl0IGRvZXMgX25vdF8KPiArCSAqIG5lY2Vz c2FyaWx5IGNvcnJlc3BvbmQgdG8gdGhlIGFjdHVhbCB0aW1pbmcgdmFsdWVzIGluIHRoZSBFTUMg YXQgdGhlCj4gKwkgKiBtb21lbnQuIElmIHRoZSBib290IEJDVCBkaWZmZXJzIGZyb20gdGhlIHRh YmxlIHRoZW4gdGhpcyBjYW4gaGFwcGVuLgo+ICsJICogSG93ZXZlciwgd2UgbmVlZCBpdCBmb3Ig YWNjZXNzaW5nIHRoZSBkcmFtX3RpbWluZ3MgKHdoaWNoIGFyZSBub3QKPiArCSAqIHJlYWxseSBy ZWdpc3RlcnMpIGFycmF5IGZvciB0aGUgY3VycmVudCBmcmVxdWVuY3kuCj4gKwkgKi8KPiArCXUz MiB0bXAsIGN5YV9hbGxvd19yZWZfY2MgPSAwLCByZWZfYjRfc3JlZl9lbiA9IDAsIGN5YV9pc3N1 ZV9wY19yZWYgPSAwOwo+ICsJc3RydWN0IHRlZ3JhMjEwX2VtY190aW1pbmcgKmZha2UsICpsYXN0 ID0gZW1jLT5sYXN0LCAqbmV4dCA9IGVtYy0+bmV4dDsKPiArCXUzMiBiZ19yZWd1bGF0b3Jfc3dp dGNoX2NvbXBsZXRlX3dhaXRfY2xrcywgYmdfcmVndWxhdG9yX21vZGVfY2hhbmdlOwo+ICsJdTMy IG9wdF96Y2FsX2VuX2NjLCBvcHRfZG9fc3dfcXJzdCA9IDEsIG9wdF9kdmZzX21vZGUsIG9wdF9k bGxfbW9kZTsKPiArCXUzMiBlbWNfemNhbF93YWl0X2NudF9vbGQsIGVtY196Y2FsX3dhaXRfY250 X25ldywgZW1jX2RiZ19hY3RpdmU7Cj4gKwl1MzIgb3B0X2NjX3Nob3J0X3pjYWwgPSAxLCBvcHRf c2hvcnRfemNhbCA9IDEsIG9wdF93YXJfMjAwMDI0OTA3Owo+ICsJdTMyIHRSVE0sIFJQX3dhciwg UjJQX3dhciwgVFJQYWJfd2FyLCBkZWx0YVRXQVRNLCBXMlBfd2FyLCB0UlBTVDsKPiArCXUzMiBh ZGVsID0gMCwgY29tcGVuc2F0ZV90cmltbWVyX2FwcGxpY2FibGUgPSAwLCBtcndfcmVxLCB2YWx1 ZTsKPiArCXVuc2lnbmVkIGxvbmcgbmV4dF90aW1pbmdfcmF0ZV9taHogPSBuZXh0LT5yYXRlIC8g MTAwMCwgZGVsYXk7Cj4gKwl1MzIgdFpRQ0FMX2xwZGRyNCA9IDEwMDAwMDAsIHpxX3dhaXRfbG9u Zywgc2hhcmVkX3pxX3Jlc2lzdG9yOwo+ICsJczMyIHpxX2xhdGNoX2R2ZnNfd2FpdF90aW1lLCB0 WlFDQUxfbHBkZHI0X2ZjX2FkaiwgblJUUDsKPiArCXUzMiB0RkNfbHBkZHI0ID0gMTAwMCAqIG5l eHQtPmRyYW1fdGltaW5nc1tUX0ZDX0xQRERSNF07Cj4gKwl1MzIgZW1jX2F1dG9fY2FsX2NvbmZp ZywgYXV0b19jYWxfZW4sIG1yMTNfY2F0cl9lbmFibGU7Cj4gKwl1MzIgenFfb3AsIHpjYWxfd2Fp dF90aW1lX2Nsb2NrcywgemNhbF93YWl0X3RpbWVfcHM7Cj4gKwl1MzIgZW1jX2NmZywgZW1jX3Nl bF9kcGRfY3RybCwgZW1jX3pjYWxfaW50ZXJ2YWw7Cj4gKwlpbnQgbmV4dF9wdXNoLCBuZXh0X2Rx X2VfaXZyZWYsIG5leHRfZHFzX2VfaXZyZWY7Cj4gKwl1MzIgbXIxM19mbGlwX2ZzcHdyLCBtcjEz X2ZsaXBfZnNwb3AsIGlzX2xwZGRyMzsKPiArCXUzMiBlbmFibGVfYmdscF9yZWd1bGF0b3IsIGVu YWJsZV9iZ19yZWd1bGF0b3I7Cj4gKwl1MzIgZW1jX2RiZ19vLCBlbWNfY2ZnX3BpcGVfY2xrX28s IGVtY19waW5fbzsKPiArCXUzMiByYW1wX3VwX3dhaXQgPSAwLCByYW1wX2Rvd25fd2FpdCA9IDA7 Cj4gKwl1MzIgc2F2ZV9yZXN0b3JlX2Nsa3N0b3BfcGQgPSAxLCBkbGxfb3V0Owo+ICsJdTMyIHJl Zl9kZWxheV9tdWx0LCByZWZfZGVsYXksIGRyYW1fdHlwZTsKPiArCXN0YXRpYyB1MzIgZnNwX2Zv cl9uZXh0X2ZyZXE7Cj4gKwkvKiBJbiBwaWNvc2Vjb25kcy4gKi8KPiArCXUzMiBzb3VyY2VfY2xv Y2tfcGVyaW9kLCBkZXN0aW5hdGlvbl9jbG9ja19wZXJpb2Q7Cj4gKwl1MzIgenFjYWxfYmVmb3Jl X2NjX2N1dG9mZiA9IDI0MDA7Cj4gKwl1bnNpZ25lZCBpbnQgaTsKCldoYXQgYWJvdXQgdG8gdHJ5 IHRvIHJlcGxhY2UgdGhpcyBtYXNzaXZlIGVneXB0aWFuIGNvbnN0cnVjdGlvbiB3aXRoIGEKc2lu Z2xlICJ1MzIgdmFsOyIgPwoKLi4uCgo+ICsJZW1jX3JlYWRsKGVtYywgRU1DX0NGRyk7Cj4gKwll bWNfYXV0b19jYWxfY29uZmlnID0gZW1jX3JlYWRsKGVtYywgRU1DX0FVVE9fQ0FMX0NPTkZJRyk7 CgpBbmQgcmVtb3ZlIGFsbCB0aGUgImR1bW15IiB2YXJpYWJsZSBhc3NpZ25zIGluIHRoZSBjb2Rl PwoKLi4uCj4gZW1jX2F1dG9fY2FsX2NvbmZpZyA9IG5leHQtPmVtY19hdXRvX2NhbF9jb25maWc7 Ci4uLj4gKwllbWNfemNhbF9pbnRlcnZhbCA9IDA7CgpBbmQgcmVwbGFjZSBhbGwgImNvbnN0YW50 IiB2YXJpYWJsZXMgd2l0aCBhIHJhdyB2YWx1ZSBpbiBwbGFjZSBpbiB0aGUgY29kZT8KCl9fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxpbnV4LWFybS1rZXJu ZWwgbWFpbGluZyBsaXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRw Oi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFybS1rZXJuZWwK