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[93.34.88.225]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a892e528a9sm2215225f8f.60.2025.06.27.02.32.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jun 2025 02:32:52 -0700 (PDT) Message-ID: <685e6544.5d0a0220.20cf55.9440@mx.google.com> X-Google-Original-Message-ID: Date: Fri, 27 Jun 2025 11:32:46 +0200 From: Christian Marangi To: Andy Shevchenko Cc: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, Benjamin Larsson , AngeloGioacchino Del Regno , Lorenzo Bianconi Subject: Re: [PATCH v18] pwm: airoha: Add support for EN7581 SoC References: <20250626224805.9034-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, Jun 27, 2025 at 11:58:04AM +0300, Andy Shevchenko wrote: > On Fri, Jun 27, 2025 at 12:47:53AM +0200, Christian Marangi wrote: > > From: Benjamin Larsson > > > > Introduce driver for PWM module available on EN7581 SoC. > > ... > > > + * Copyright 2025 Markus Gothe > > + * Christian Marangi > > I'm not sure you can change the copyright line like this. I would rather expect > > * Copyright 2012 Markus Gothe > * Copyright 2025 Christian Marangi > > (Sorry, I forgot the exact original year there, but you got the point) > > ... > > > + /* Global mutex to protect bucket used refcount_t */ > > + struct mutex mutex; > > This makes a little sense. Either you use refcount_t (which is atomic) or > use mutex + regular variable. > Using a regular variable I lose all the benefits of refcount_t with underflow and other checks. > ... > > > + /* > > + * It is necessary to explicitly shift out all zeros after muxing > > + * to initialize the shift register before enabling PWM > > + * mode because in PWM mode SIPO will not start shifting until > > + * it needs to output a non-zero value (bit 31 of led_data > > + * indicates shifting in progress and it must return to zero > > + * before led_data can be written or PWM mode can be set) > > Missing period at the end. > > > + */ > > ... > > > +static void airoha_pwm_disable(struct airoha_pwm *pc, struct pwm_device *pwm) > > +{ > > + /* Disable PWM and release the bucket */ > > + airoha_pwm_config_flash_map(pc, pwm->hwpwm, -1); > > + airoha_pwm_release_bucket_config(pc, pwm->hwpwm); > > + > > + clear_bit(pwm->hwpwm, pc->initialized); > > + > > + /* If no SIPO is used, disable the shift register chip */ > > + if (find_next_bit(pc->initialized, AIROHA_PWM_MAX_CHANNELS, > > + AIROHA_PWM_NUM_GPIO) >= AIROHA_PWM_NUM_GPIO) > > This can be rewritten as > > if (!bitmap_read(pc->initialized, AIROHA_PWM_NUM_GPIO, AIROHA_PWM_NUM_SIPO)) > > (seems to me that the above code is buggy and has to have a check against the > full size of bitmap). > Yes I'm confused by find_next_bit. Is the nbits part the rest of the bit or the full size of the bitmap? Google suggest it should be the full size of the bitmap but I wasn't so sure. Anyway I will use bitmap_read since it seems more readable. > > + regmap_clear_bits(pc->regmap, AIROHA_PWM_REG_SIPO_FLASH_MODE_CFG, > > + AIROHA_PWM_SERIAL_GPIO_FLASH_MODE); > > +} > > -- > With Best Regards, > Andy Shevchenko > > -- Ansuel