diff for duplicates of <68719599.130141448266183403.JavaMail.weblogic@epmlwas06a> diff --git a/a/1.txt b/N1/1.txt index 20b7774..daf7181 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,28 +1,47 @@ -PiArc3RhdGljIHVuc2lnbmVkIGxvbmcgcmszMzk5X2RtY2Nsa19yZWNhbGNfcmF0ZShzdHJ1Y3Qg -Y2xrX2h3ICpodywNCj4gKwkJCQkJICAgICAgIHVuc2lnbmVkIGxvbmcgcGFyZW50X3JhdGUpDQo+ -ICt7DQo+ICsJc3RydWN0IHJrMzM5OV9kbWNjbGsgKmRtYyA9IHRvX3JrMzM5OV9kbWNjbGsoJmh3 -KTsNCj4gKwl1MzIgdmFsOw0KPiArDQo+ICsJLyoNCj4gKwkgKiBHZXQgcGFyZW50IHJhdGUgc2lu -Y2UgaXQgY2hhbmdlZCBpbiB0aGlzIGNsa3Mgc2V0X3JhdGUgb3AuIFRoZSBwYXJlbnQNCj4gKwkg -KiByYXRlIHBhc3NlZCBpbnRvIHRoaXMgZnVuY3Rpb24gaXMgY2FjaGVkIGJlZm9yZSBzZXRfcmF0 -ZSBpcyBjYWxsZWQgaW4NCj4gKwkgKiB0aGUgY29tbW9uIGNsayBjb2RlLCBzbyB3ZSBoYXZlIHRv -IGdldCBpdCBoZXJlLg0KPiArCSAqLw0KPiArCXBhcmVudF9yYXRlID0gY2xrX2dldF9yYXRlKGNs -a19nZXRfcGFyZW50KGh3LT5jbGspKTsNCj4gKw0KPiArCXZhbCA9IHJlYWRsKGRtYy0+Y3J1ICsg -Q1JVX0NMS1NFTDZfQ09OKTsNCj4gKwl2YWwgPSAodmFsID4+IENMS19ERFJDX0RJVl9DT05fU0hJ -RlQpICYgQ0xLX0REUkNfRElWX0NPTl9NQVNLOw0KPiArDQo+ICsJcmV0dXJuIHBhcmVudF9yYXRl -IC8gKHZhbCArIDEpOw0KPiArfQ0KPiArDQo+ICsvKg0KPiArICogVE9ETzogc2V0IGRkciBmcmVx -dWNuZXkgaW4gZGNmIHdoaWNoIHJ1biBpbiBBVEYNCj4gKyAqLw0KPiArc3RhdGljIGludCByazMz -OTlfZG1jY2xrX3NldF9yYXRlKHN0cnVjdCBjbGtfaHcgKmh3LCB1bnNpZ25lZCBsb25nIHJhdGUs -DQo+ICsJCQkJICB1bnNpZ25lZCBsb25nIHBhcmVudF9yYXRlKQ0KPiArew0KPiArCXJldHVybiAw -Ow0KPiArfQ0KDQpJcyBpdCBjb3JyZWN0IHRoYXQgeW91IGRpZG4ndCBmaWxsIHRoaXMgdXAgYmVj -YXVzZSB5b3VyDQpUcnVzdHpvbmUgZHJpdmVyIChTTUMpIGlzIG5vdCByZWFkeSB5ZXQ/DQoNClRo -ZW4sIHdoeSBkb24ndCB5b3UgZmlsbCB0aGF0IGZ1bmN0aW9uIGFzc3VtaW5nIHRoYXQgVHJ1c3Ra -b25lIGlzIG5vdCBhY3RpdmF0ZWQNCmFuZCBhZGQgU01DIGNhbGwgZnVuY3Rpb25zIHdpdGggaWYg -b3IgI2lmIGFmdGVyIGl0cyBUcnVzdFpvbmUgZHJpdmVyIGlzIHJlYWR5Pw0KDQpPciBkb2VzIHlv -dXIgU29DIG1hbmRhdGUgdGhlIHVzYWdlIG90IFRydXN0Wm9uZSwgcmVzdHJpY3RpbmcgdGhlIHVz -YWdlDQpvZiBDUlVfQ0xLU0VMNl9DT04gd3JpdGU/IChJIGRvbid0IHNlZSB3aHkgU29DIHZlbmRv -cnMgd2lsbCBkbyB0aGlzLi4pDQoNCg0KSSdsbCBiZSByZWFkeSB0byBtZXJnZSB0aGUgUkszMzk5 -IGRldmZyZXEgZHJpdmVyIGlmIHlvdQ0KZmlsbCB0aGlzIHVwIChhc3N1bWluZyB0aGF0IFRaIGlz -IG5vdCBlbmFibGVkKSBvcg0KYWRkIFRaIGRyaXZlciBhbmQgU01DIGNhbGxzLg0KDQoNCkNoZWVy -cywNCk15dW5nSm9vDQpwcy4gYWNjb3JkaW5nIHRvIHJrMzM5X2RtY2Nsa19yZWNhbGNfcmF0ZSgp -LCBmaWxsaW5nIHJrMzM5X2RtY2Nsa19zZXRfcmF0ZQ0KYXNzdW1pbmcgdGhhdCBUWiBpcyBub3Qg -ZW5hYmxlZCBzZWVtcyB0cml2aWFsLg== +> +static unsigned long rk3399_dmcclk_recalc_rate(struct clk_hw *hw, +> + unsigned long parent_rate) +> +{ +> + struct rk3399_dmcclk *dmc = to_rk3399_dmcclk(&hw); +> + u32 val; +> + +> + /* +> + * Get parent rate since it changed in this clks set_rate op. The parent +> + * rate passed into this function is cached before set_rate is called in +> + * the common clk code, so we have to get it here. +> + */ +> + parent_rate = clk_get_rate(clk_get_parent(hw->clk)); +> + +> + val = readl(dmc->cru + CRU_CLKSEL6_CON); +> + val = (val >> CLK_DDRC_DIV_CON_SHIFT) & CLK_DDRC_DIV_CON_MASK; +> + +> + return parent_rate / (val + 1); +> +} +> + +> +/* +> + * TODO: set ddr frequcney in dcf which run in ATF +> + */ +> +static int rk3399_dmcclk_set_rate(struct clk_hw *hw, unsigned long rate, +> + unsigned long parent_rate) +> +{ +> + return 0; +> +} + +Is it correct that you didn't fill this up because your +Trustzone driver (SMC) is not ready yet? + +Then, why don't you fill that function assuming that TrustZone is not activated +and add SMC call functions with if or #if after its TrustZone driver is ready? + +Or does your SoC mandate the usage ot TrustZone, restricting the usage +of CRU_CLKSEL6_CON write? (I don't see why SoC vendors will do this..) + + +I'll be ready to merge the RK3399 devfreq driver if you +fill this up (assuming that TZ is not enabled) or +add TZ driver and SMC calls. + + +Cheers, +MyungJoo +ps. according to rk339_dmcclk_recalc_rate(), filling rk339_dmcclk_set_rate +assuming that TZ is not enabled seems trivial. diff --git a/a/content_digest b/N1/content_digest index da70c35..32acde7 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -13,33 +13,52 @@ " linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>\0" "\00:1\0" "b\0" - "PiArc3RhdGljIHVuc2lnbmVkIGxvbmcgcmszMzk5X2RtY2Nsa19yZWNhbGNfcmF0ZShzdHJ1Y3Qg\n" - "Y2xrX2h3ICpodywNCj4gKwkJCQkJICAgICAgIHVuc2lnbmVkIGxvbmcgcGFyZW50X3JhdGUpDQo+\n" - "ICt7DQo+ICsJc3RydWN0IHJrMzM5OV9kbWNjbGsgKmRtYyA9IHRvX3JrMzM5OV9kbWNjbGsoJmh3\n" - "KTsNCj4gKwl1MzIgdmFsOw0KPiArDQo+ICsJLyoNCj4gKwkgKiBHZXQgcGFyZW50IHJhdGUgc2lu\n" - "Y2UgaXQgY2hhbmdlZCBpbiB0aGlzIGNsa3Mgc2V0X3JhdGUgb3AuIFRoZSBwYXJlbnQNCj4gKwkg\n" - "KiByYXRlIHBhc3NlZCBpbnRvIHRoaXMgZnVuY3Rpb24gaXMgY2FjaGVkIGJlZm9yZSBzZXRfcmF0\n" - "ZSBpcyBjYWxsZWQgaW4NCj4gKwkgKiB0aGUgY29tbW9uIGNsayBjb2RlLCBzbyB3ZSBoYXZlIHRv\n" - "IGdldCBpdCBoZXJlLg0KPiArCSAqLw0KPiArCXBhcmVudF9yYXRlID0gY2xrX2dldF9yYXRlKGNs\n" - "a19nZXRfcGFyZW50KGh3LT5jbGspKTsNCj4gKw0KPiArCXZhbCA9IHJlYWRsKGRtYy0+Y3J1ICsg\n" - "Q1JVX0NMS1NFTDZfQ09OKTsNCj4gKwl2YWwgPSAodmFsID4+IENMS19ERFJDX0RJVl9DT05fU0hJ\n" - "RlQpICYgQ0xLX0REUkNfRElWX0NPTl9NQVNLOw0KPiArDQo+ICsJcmV0dXJuIHBhcmVudF9yYXRl\n" - "IC8gKHZhbCArIDEpOw0KPiArfQ0KPiArDQo+ICsvKg0KPiArICogVE9ETzogc2V0IGRkciBmcmVx\n" - "dWNuZXkgaW4gZGNmIHdoaWNoIHJ1biBpbiBBVEYNCj4gKyAqLw0KPiArc3RhdGljIGludCByazMz\n" - "OTlfZG1jY2xrX3NldF9yYXRlKHN0cnVjdCBjbGtfaHcgKmh3LCB1bnNpZ25lZCBsb25nIHJhdGUs\n" - "DQo+ICsJCQkJICB1bnNpZ25lZCBsb25nIHBhcmVudF9yYXRlKQ0KPiArew0KPiArCXJldHVybiAw\n" - "Ow0KPiArfQ0KDQpJcyBpdCBjb3JyZWN0IHRoYXQgeW91IGRpZG4ndCBmaWxsIHRoaXMgdXAgYmVj\n" - "YXVzZSB5b3VyDQpUcnVzdHpvbmUgZHJpdmVyIChTTUMpIGlzIG5vdCByZWFkeSB5ZXQ/DQoNClRo\n" - "ZW4sIHdoeSBkb24ndCB5b3UgZmlsbCB0aGF0IGZ1bmN0aW9uIGFzc3VtaW5nIHRoYXQgVHJ1c3Ra\n" - "b25lIGlzIG5vdCBhY3RpdmF0ZWQNCmFuZCBhZGQgU01DIGNhbGwgZnVuY3Rpb25zIHdpdGggaWYg\n" - "b3IgI2lmIGFmdGVyIGl0cyBUcnVzdFpvbmUgZHJpdmVyIGlzIHJlYWR5Pw0KDQpPciBkb2VzIHlv\n" - "dXIgU29DIG1hbmRhdGUgdGhlIHVzYWdlIG90IFRydXN0Wm9uZSwgcmVzdHJpY3RpbmcgdGhlIHVz\n" - "YWdlDQpvZiBDUlVfQ0xLU0VMNl9DT04gd3JpdGU/IChJIGRvbid0IHNlZSB3aHkgU29DIHZlbmRv\n" - "cnMgd2lsbCBkbyB0aGlzLi4pDQoNCg0KSSdsbCBiZSByZWFkeSB0byBtZXJnZSB0aGUgUkszMzk5\n" - "IGRldmZyZXEgZHJpdmVyIGlmIHlvdQ0KZmlsbCB0aGlzIHVwIChhc3N1bWluZyB0aGF0IFRaIGlz\n" - "IG5vdCBlbmFibGVkKSBvcg0KYWRkIFRaIGRyaXZlciBhbmQgU01DIGNhbGxzLg0KDQoNCkNoZWVy\n" - "cywNCk15dW5nSm9vDQpwcy4gYWNjb3JkaW5nIHRvIHJrMzM5X2RtY2Nsa19yZWNhbGNfcmF0ZSgp\n" - "LCBmaWxsaW5nIHJrMzM5X2RtY2Nsa19zZXRfcmF0ZQ0KYXNzdW1pbmcgdGhhdCBUWiBpcyBub3Qg\n" - ZW5hYmxlZCBzZWVtcyB0cml2aWFsLg== + "> +static unsigned long rk3399_dmcclk_recalc_rate(struct clk_hw *hw,\n" + "> +\t\t\t\t\t unsigned long parent_rate)\n" + "> +{\n" + "> +\tstruct rk3399_dmcclk *dmc = to_rk3399_dmcclk(&hw);\n" + "> +\tu32 val;\n" + "> +\n" + "> +\t/*\n" + "> +\t * Get parent rate since it changed in this clks set_rate op. The parent\n" + "> +\t * rate passed into this function is cached before set_rate is called in\n" + "> +\t * the common clk code, so we have to get it here.\n" + "> +\t */\n" + "> +\tparent_rate = clk_get_rate(clk_get_parent(hw->clk));\n" + "> +\n" + "> +\tval = readl(dmc->cru + CRU_CLKSEL6_CON);\n" + "> +\tval = (val >> CLK_DDRC_DIV_CON_SHIFT) & CLK_DDRC_DIV_CON_MASK;\n" + "> +\n" + "> +\treturn parent_rate / (val + 1);\n" + "> +}\n" + "> +\n" + "> +/*\n" + "> + * TODO: set ddr frequcney in dcf which run in ATF\n" + "> + */\n" + "> +static int rk3399_dmcclk_set_rate(struct clk_hw *hw, unsigned long rate,\n" + "> +\t\t\t\t unsigned long parent_rate)\n" + "> +{\n" + "> +\treturn 0;\n" + "> +}\n" + "\n" + "Is it correct that you didn't fill this up because your\n" + "Trustzone driver (SMC) is not ready yet?\n" + "\n" + "Then, why don't you fill that function assuming that TrustZone is not activated\n" + "and add SMC call functions with if or #if after its TrustZone driver is ready?\n" + "\n" + "Or does your SoC mandate the usage ot TrustZone, restricting the usage\n" + "of CRU_CLKSEL6_CON write? (I don't see why SoC vendors will do this..)\n" + "\n" + "\n" + "I'll be ready to merge the RK3399 devfreq driver if you\n" + "fill this up (assuming that TZ is not enabled) or\n" + "add TZ driver and SMC calls.\n" + "\n" + "\n" + "Cheers,\n" + "MyungJoo\n" + "ps. according to rk339_dmcclk_recalc_rate(), filling rk339_dmcclk_set_rate\n" + assuming that TZ is not enabled seems trivial. -192963f3ab47d5f10e9555106a6968457a37f667040d2fa3edd5e58e3edf4019 +26e66e6eb1d60897ab8b6281c56f834ae3af3f6a1583915f1cca898b8b0bd8c5
diff --git a/a/1.txt b/N2/1.txt index 20b7774..b4e3ee1 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,28 +1,47 @@ -PiArc3RhdGljIHVuc2lnbmVkIGxvbmcgcmszMzk5X2RtY2Nsa19yZWNhbGNfcmF0ZShzdHJ1Y3Qg -Y2xrX2h3ICpodywNCj4gKwkJCQkJICAgICAgIHVuc2lnbmVkIGxvbmcgcGFyZW50X3JhdGUpDQo+ -ICt7DQo+ICsJc3RydWN0IHJrMzM5OV9kbWNjbGsgKmRtYyA9IHRvX3JrMzM5OV9kbWNjbGsoJmh3 -KTsNCj4gKwl1MzIgdmFsOw0KPiArDQo+ICsJLyoNCj4gKwkgKiBHZXQgcGFyZW50IHJhdGUgc2lu -Y2UgaXQgY2hhbmdlZCBpbiB0aGlzIGNsa3Mgc2V0X3JhdGUgb3AuIFRoZSBwYXJlbnQNCj4gKwkg -KiByYXRlIHBhc3NlZCBpbnRvIHRoaXMgZnVuY3Rpb24gaXMgY2FjaGVkIGJlZm9yZSBzZXRfcmF0 -ZSBpcyBjYWxsZWQgaW4NCj4gKwkgKiB0aGUgY29tbW9uIGNsayBjb2RlLCBzbyB3ZSBoYXZlIHRv -IGdldCBpdCBoZXJlLg0KPiArCSAqLw0KPiArCXBhcmVudF9yYXRlID0gY2xrX2dldF9yYXRlKGNs -a19nZXRfcGFyZW50KGh3LT5jbGspKTsNCj4gKw0KPiArCXZhbCA9IHJlYWRsKGRtYy0+Y3J1ICsg -Q1JVX0NMS1NFTDZfQ09OKTsNCj4gKwl2YWwgPSAodmFsID4+IENMS19ERFJDX0RJVl9DT05fU0hJ -RlQpICYgQ0xLX0REUkNfRElWX0NPTl9NQVNLOw0KPiArDQo+ICsJcmV0dXJuIHBhcmVudF9yYXRl -IC8gKHZhbCArIDEpOw0KPiArfQ0KPiArDQo+ICsvKg0KPiArICogVE9ETzogc2V0IGRkciBmcmVx -dWNuZXkgaW4gZGNmIHdoaWNoIHJ1biBpbiBBVEYNCj4gKyAqLw0KPiArc3RhdGljIGludCByazMz -OTlfZG1jY2xrX3NldF9yYXRlKHN0cnVjdCBjbGtfaHcgKmh3LCB1bnNpZ25lZCBsb25nIHJhdGUs -DQo+ICsJCQkJICB1bnNpZ25lZCBsb25nIHBhcmVudF9yYXRlKQ0KPiArew0KPiArCXJldHVybiAw -Ow0KPiArfQ0KDQpJcyBpdCBjb3JyZWN0IHRoYXQgeW91IGRpZG4ndCBmaWxsIHRoaXMgdXAgYmVj -YXVzZSB5b3VyDQpUcnVzdHpvbmUgZHJpdmVyIChTTUMpIGlzIG5vdCByZWFkeSB5ZXQ/DQoNClRo -ZW4sIHdoeSBkb24ndCB5b3UgZmlsbCB0aGF0IGZ1bmN0aW9uIGFzc3VtaW5nIHRoYXQgVHJ1c3Ra -b25lIGlzIG5vdCBhY3RpdmF0ZWQNCmFuZCBhZGQgU01DIGNhbGwgZnVuY3Rpb25zIHdpdGggaWYg -b3IgI2lmIGFmdGVyIGl0cyBUcnVzdFpvbmUgZHJpdmVyIGlzIHJlYWR5Pw0KDQpPciBkb2VzIHlv -dXIgU29DIG1hbmRhdGUgdGhlIHVzYWdlIG90IFRydXN0Wm9uZSwgcmVzdHJpY3RpbmcgdGhlIHVz -YWdlDQpvZiBDUlVfQ0xLU0VMNl9DT04gd3JpdGU/IChJIGRvbid0IHNlZSB3aHkgU29DIHZlbmRv -cnMgd2lsbCBkbyB0aGlzLi4pDQoNCg0KSSdsbCBiZSByZWFkeSB0byBtZXJnZSB0aGUgUkszMzk5 -IGRldmZyZXEgZHJpdmVyIGlmIHlvdQ0KZmlsbCB0aGlzIHVwIChhc3N1bWluZyB0aGF0IFRaIGlz -IG5vdCBlbmFibGVkKSBvcg0KYWRkIFRaIGRyaXZlciBhbmQgU01DIGNhbGxzLg0KDQoNCkNoZWVy -cywNCk15dW5nSm9vDQpwcy4gYWNjb3JkaW5nIHRvIHJrMzM5X2RtY2Nsa19yZWNhbGNfcmF0ZSgp -LCBmaWxsaW5nIHJrMzM5X2RtY2Nsa19zZXRfcmF0ZQ0KYXNzdW1pbmcgdGhhdCBUWiBpcyBub3Qg -ZW5hYmxlZCBzZWVtcyB0cml2aWFsLg== +> +static unsigned long rk3399_dmcclk_recalc_rate(struct clk_hw *hw, +> + unsigned long parent_rate) +> +{ +> + struct rk3399_dmcclk *dmc = to_rk3399_dmcclk(&hw); +> + u32 val; +> + +> + /* +> + * Get parent rate since it changed in this clks set_rate op. The parent +> + * rate passed into this function is cached before set_rate is called in +> + * the common clk code, so we have to get it here. +> + */ +> + parent_rate = clk_get_rate(clk_get_parent(hw->clk)); +> + +> + val = readl(dmc->cru + CRU_CLKSEL6_CON); +> + val = (val >> CLK_DDRC_DIV_CON_SHIFT) & CLK_DDRC_DIV_CON_MASK; +> + +> + return parent_rate / (val + 1); +> +} +> + +> +/* +> + * TODO: set ddr frequcney in dcf which run in ATF +> + */ +> +static int rk3399_dmcclk_set_rate(struct clk_hw *hw, unsigned long rate, +> + unsigned long parent_rate) +> +{ +> + return 0; +> +} + +Is it correct that you didn't fill this up because your +Trustzone driver (SMC) is not ready yet? + +Then, why don't you fill that function assuming that TrustZone is not activated +and add SMC call functions with if or #if after its TrustZone driver is ready? + +Or does your SoC mandate the usage ot TrustZone, restricting the usage +of CRU_CLKSEL6_CON write? (I don't see why SoC vendors will do this..) + + +I'll be ready to merge the RK3399 devfreq driver if you +fill this up (assuming that TZ is not enabled) or +add TZ driver and SMC calls. + + +Cheers, +MyungJoo +ps. according to rk339_dmcclk_recalc_rate(), filling rk339_dmcclk_set_rate +assuming that TZ is not enabled seems trivial.ÿôèº{.nÇ+‰·Ÿ®‰†+%ŠËÿ±éݶ\x17¥Šwÿº{.nÇ+‰·¥Š{±þG«éÿŠ{ayº\x1dʇڙë,j\a¢f£¢·hšïêÿ‘êçz_è®\x03(階ŠÝ¢j"ú\x1a¶^[m§ÿÿ¾\a«þG«éÿ¢¸?™¨èÚ&£ø§~á¶iO•æ¬z·švØ^\x14\x04\x1a¶^[m§ÿÿÃ\fÿ¶ìÿ¢¸?–I¥ diff --git a/a/content_digest b/N2/content_digest index da70c35..aa9a79e 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,6 +1,6 @@ "From\0MyungJoo Ham <myungjoo.ham@samsung.com>\0" "Subject\0Re: [PATCH 1/2] clk: rockchip: dmc: support rk3399 dmc clock driver\0" - "Date\0Mon, 23 Nov 2015 08:09:45 +0000 (GMT)\0" + "Date\0Mon, 23 Nov 2015 08:09:47 +0000 (GMT)\0" "To\0Lin Huang <hl@rock-chips.com>" heiko@sntech.de <heiko@sntech.de> dianders@chromium.org <dianders@chromium.org> @@ -13,33 +13,52 @@ " linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>\0" "\00:1\0" "b\0" - "PiArc3RhdGljIHVuc2lnbmVkIGxvbmcgcmszMzk5X2RtY2Nsa19yZWNhbGNfcmF0ZShzdHJ1Y3Qg\n" - "Y2xrX2h3ICpodywNCj4gKwkJCQkJICAgICAgIHVuc2lnbmVkIGxvbmcgcGFyZW50X3JhdGUpDQo+\n" - "ICt7DQo+ICsJc3RydWN0IHJrMzM5OV9kbWNjbGsgKmRtYyA9IHRvX3JrMzM5OV9kbWNjbGsoJmh3\n" - "KTsNCj4gKwl1MzIgdmFsOw0KPiArDQo+ICsJLyoNCj4gKwkgKiBHZXQgcGFyZW50IHJhdGUgc2lu\n" - "Y2UgaXQgY2hhbmdlZCBpbiB0aGlzIGNsa3Mgc2V0X3JhdGUgb3AuIFRoZSBwYXJlbnQNCj4gKwkg\n" - "KiByYXRlIHBhc3NlZCBpbnRvIHRoaXMgZnVuY3Rpb24gaXMgY2FjaGVkIGJlZm9yZSBzZXRfcmF0\n" - "ZSBpcyBjYWxsZWQgaW4NCj4gKwkgKiB0aGUgY29tbW9uIGNsayBjb2RlLCBzbyB3ZSBoYXZlIHRv\n" - "IGdldCBpdCBoZXJlLg0KPiArCSAqLw0KPiArCXBhcmVudF9yYXRlID0gY2xrX2dldF9yYXRlKGNs\n" - "a19nZXRfcGFyZW50KGh3LT5jbGspKTsNCj4gKw0KPiArCXZhbCA9IHJlYWRsKGRtYy0+Y3J1ICsg\n" - "Q1JVX0NMS1NFTDZfQ09OKTsNCj4gKwl2YWwgPSAodmFsID4+IENMS19ERFJDX0RJVl9DT05fU0hJ\n" - "RlQpICYgQ0xLX0REUkNfRElWX0NPTl9NQVNLOw0KPiArDQo+ICsJcmV0dXJuIHBhcmVudF9yYXRl\n" - "IC8gKHZhbCArIDEpOw0KPiArfQ0KPiArDQo+ICsvKg0KPiArICogVE9ETzogc2V0IGRkciBmcmVx\n" - "dWNuZXkgaW4gZGNmIHdoaWNoIHJ1biBpbiBBVEYNCj4gKyAqLw0KPiArc3RhdGljIGludCByazMz\n" - "OTlfZG1jY2xrX3NldF9yYXRlKHN0cnVjdCBjbGtfaHcgKmh3LCB1bnNpZ25lZCBsb25nIHJhdGUs\n" - "DQo+ICsJCQkJICB1bnNpZ25lZCBsb25nIHBhcmVudF9yYXRlKQ0KPiArew0KPiArCXJldHVybiAw\n" - "Ow0KPiArfQ0KDQpJcyBpdCBjb3JyZWN0IHRoYXQgeW91IGRpZG4ndCBmaWxsIHRoaXMgdXAgYmVj\n" - "YXVzZSB5b3VyDQpUcnVzdHpvbmUgZHJpdmVyIChTTUMpIGlzIG5vdCByZWFkeSB5ZXQ/DQoNClRo\n" - "ZW4sIHdoeSBkb24ndCB5b3UgZmlsbCB0aGF0IGZ1bmN0aW9uIGFzc3VtaW5nIHRoYXQgVHJ1c3Ra\n" - "b25lIGlzIG5vdCBhY3RpdmF0ZWQNCmFuZCBhZGQgU01DIGNhbGwgZnVuY3Rpb25zIHdpdGggaWYg\n" - "b3IgI2lmIGFmdGVyIGl0cyBUcnVzdFpvbmUgZHJpdmVyIGlzIHJlYWR5Pw0KDQpPciBkb2VzIHlv\n" - "dXIgU29DIG1hbmRhdGUgdGhlIHVzYWdlIG90IFRydXN0Wm9uZSwgcmVzdHJpY3RpbmcgdGhlIHVz\n" - "YWdlDQpvZiBDUlVfQ0xLU0VMNl9DT04gd3JpdGU/IChJIGRvbid0IHNlZSB3aHkgU29DIHZlbmRv\n" - "cnMgd2lsbCBkbyB0aGlzLi4pDQoNCg0KSSdsbCBiZSByZWFkeSB0byBtZXJnZSB0aGUgUkszMzk5\n" - "IGRldmZyZXEgZHJpdmVyIGlmIHlvdQ0KZmlsbCB0aGlzIHVwIChhc3N1bWluZyB0aGF0IFRaIGlz\n" - "IG5vdCBlbmFibGVkKSBvcg0KYWRkIFRaIGRyaXZlciBhbmQgU01DIGNhbGxzLg0KDQoNCkNoZWVy\n" - "cywNCk15dW5nSm9vDQpwcy4gYWNjb3JkaW5nIHRvIHJrMzM5X2RtY2Nsa19yZWNhbGNfcmF0ZSgp\n" - "LCBmaWxsaW5nIHJrMzM5X2RtY2Nsa19zZXRfcmF0ZQ0KYXNzdW1pbmcgdGhhdCBUWiBpcyBub3Qg\n" - ZW5hYmxlZCBzZWVtcyB0cml2aWFsLg== + "> +static unsigned long rk3399_dmcclk_recalc_rate(struct clk_hw *hw,\n" + "> +\t\t\t\t\t unsigned long parent_rate)\n" + "> +{\n" + "> +\tstruct rk3399_dmcclk *dmc = to_rk3399_dmcclk(&hw);\n" + "> +\tu32 val;\n" + "> +\n" + "> +\t/*\n" + "> +\t * Get parent rate since it changed in this clks set_rate op. The parent\n" + "> +\t * rate passed into this function is cached before set_rate is called in\n" + "> +\t * the common clk code, so we have to get it here.\n" + "> +\t */\n" + "> +\tparent_rate = clk_get_rate(clk_get_parent(hw->clk));\n" + "> +\n" + "> +\tval = readl(dmc->cru + CRU_CLKSEL6_CON);\n" + "> +\tval = (val >> CLK_DDRC_DIV_CON_SHIFT) & CLK_DDRC_DIV_CON_MASK;\n" + "> +\n" + "> +\treturn parent_rate / (val + 1);\n" + "> +}\n" + "> +\n" + "> +/*\n" + "> + * TODO: set ddr frequcney in dcf which run in ATF\n" + "> + */\n" + "> +static int rk3399_dmcclk_set_rate(struct clk_hw *hw, unsigned long rate,\n" + "> +\t\t\t\t unsigned long parent_rate)\n" + "> +{\n" + "> +\treturn 0;\n" + "> +}\n" + "\n" + "Is it correct that you didn't fill this up because your\n" + "Trustzone driver (SMC) is not ready yet?\n" + "\n" + "Then, why don't you fill that function assuming that TrustZone is not activated\n" + "and add SMC call functions with if or #if after its TrustZone driver is ready?\n" + "\n" + "Or does your SoC mandate the usage ot TrustZone, restricting the usage\n" + "of CRU_CLKSEL6_CON write? (I don't see why SoC vendors will do this..)\n" + "\n" + "\n" + "I'll be ready to merge the RK3399 devfreq driver if you\n" + "fill this up (assuming that TZ is not enabled) or\n" + "add TZ driver and SMC calls.\n" + "\n" + "\n" + "Cheers,\n" + "MyungJoo\n" + "ps. according to rk339_dmcclk_recalc_rate(), filling rk339_dmcclk_set_rate\n" + "assuming that TZ is not enabled seems trivial.\303\277\303\264\303\250\302\272{.n\303\207+\302\211\302\267\302\237\302\256\302\211\302\255\302\206+%\302\212\303\213\303\277\302\261\303\251\303\235\302\266\027\302\245\302\212w\303\277\302\272{.n\303\207+\302\211\302\267\302\245\302\212{\302\261\303\276G\302\253\302\235\303\251\303\277\302\212{ay\302\272\035\303\212\302\207\303\232\302\231\303\253,j\a\302\255\302\242f\302\243\302\242\302\267h\302\232\302\217\303\257\302\201\303\252\303\277\302\221\303\252\303\247z_\303\250\302\256\003(\302\255\303\251\302\232\302\216\302\212\303\235\302\242j\"\302\235\303\272\032\302\266\033m\302\247\303\277\303\277\302\276\a\302\253\303\276G\302\253\302\235\303\251\303\277\302\242\302\270?\302\231\302\250\303\250\302\255\303\232&\302\243\303\270\302\247~\302\217\303\241\302\266iO\302\225\303\246\302\254z\302\267\302\232v\303\230^\024\004\032\302\266\033m\302\247\303\277\303\277\303\203\f\303\277\302\266\303\254\303\277\302\242\302\270?\302\226I\302\245" -192963f3ab47d5f10e9555106a6968457a37f667040d2fa3edd5e58e3edf4019 +efd55ffc54bbbf835ae2aea34743927637b0943498cdb86bd77bff34f6735ca9
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