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([176.200.63.230]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-458639ffca5sm21695845e9.1.2025.07.22.12.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Jul 2025 12:00:37 -0700 (PDT) Message-ID: <687fdfd5.050a0220.29df4a.b412@mx.google.com> X-Google-Original-Message-ID: Date: Tue, 22 Jul 2025 21:00:36 +0200 From: Christian Marangi To: Tom Rini , Ryder Lee , Weijie Gao , Chunfeng Yun , GSS_MTK_Uboot_upstream , u-boot@lists.denx.de Subject: Re: [PATCH 2/2] airoha: rework RAM size handling to support multiple RAM size References: <20250716073716.11698-1-ansuelsmth@gmail.com> <20250716073716.11698-2-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250716073716.11698-2-ansuelsmth@gmail.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On Wed, Jul 16, 2025 at 09:37:08AM +0200, Christian Marangi wrote: > There are multiple version of the same reference board with different > RAM size and it's not enough to base the RAM size entirely from DT. To > better support it use the get_ram_size way to scan for the actual RAM > size of Airoha SoC and increase the size of the memory map. > > Signed-off-by: Christian Marangi Sorry ignore this as it was sent by mistake, I resent a new version of the same patch that actually apply and build. > --- > arch/arm/mach-airoha/an7581/init.c | 22 ++++++++++++++++++---- > arch/arm/mach-airoha/an7583/init.c | 22 ++++++++++++++++++---- > 2 files changed, 36 insertions(+), 8 deletions(-) > > diff --git a/arch/arm/mach-airoha/an7581/init.c b/arch/arm/mach-airoha/an7581/init.c > index cefe9c6db9e..caf1006b22b 100644 > --- a/arch/arm/mach-airoha/an7581/init.c > +++ b/arch/arm/mach-airoha/an7581/init.c > @@ -3,8 +3,11 @@ > #include > #include > #include > +#include > #include > > +DECLARE_GLOBAL_DATA_PTR; > + > int print_cpuinfo(void) > { > printf("CPU: Airoha AN7581\n"); > @@ -13,12 +16,23 @@ int print_cpuinfo(void) > > int dram_init(void) > { > - return fdtdec_setup_mem_size_base(); > + int ret; > + > + ret = fdtdec_setup_mem_size_base(); > + if (ret) > + return ret; > + > + gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G); > + > + return 0; > } > > int dram_init_banksize(void) > { > - return fdtdec_setup_memory_banksize(); > + gd->bd->bi_dram[0].start = gd->ram_base; > + gd->bd->bi_dram[0].size = gd->ram_size; > + > + return 0; > } > > void reset_cpu(ulong addr) > @@ -31,12 +45,12 @@ static struct mm_region an7581_mem_map[] = { > /* DDR */ > .virt = 0x80000000UL, > .phys = 0x80000000UL, > - .size = 0x80000000UL, > + .size = 0x200000000ULL, > .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, > }, { > .virt = 0x00000000UL, > .phys = 0x00000000UL, > - .size = 0x20000000UL, > + .size = 0x40000000UL, > .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > PTE_BLOCK_NON_SHARE | > PTE_BLOCK_PXN | PTE_BLOCK_UXN > diff --git a/arch/arm/mach-airoha/an7583/init.c b/arch/arm/mach-airoha/an7583/init.c > index 77c29290331..c00837b4234 100644 > --- a/arch/arm/mach-airoha/an7583/init.c > +++ b/arch/arm/mach-airoha/an7583/init.c > @@ -4,6 +4,9 @@ > #include > #include > #include > +#include > + > +DECLARE_GLOBAL_DATA_PTR; > > int print_cpuinfo(void) > { > @@ -13,12 +16,23 @@ int print_cpuinfo(void) > > int dram_init(void) > { > - return fdtdec_setup_mem_size_base(); > + int ret; > + > + ret = fdtdec_setup_mem_size_base(); > + if (ret) > + return ret; > + > + gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_8G); > + > + return 0; > } > > int dram_init_banksize(void) > { > - return fdtdec_setup_memory_banksize(); > + gd->bd->bi_dram[0].start = gd->ram_base; > + gd->bd->bi_dram[0].size = gd->ram_size; > + > + return 0; > } > > void reset_cpu(ulong addr) > @@ -31,12 +45,12 @@ static struct mm_region an7583_mem_map[] = { > /* DDR */ > .virt = 0x80000000UL, > .phys = 0x80000000UL, > - .size = 0x80000000UL, > + .size = 0x200000000ULL, > .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, > }, { > .virt = 0x00000000UL, > .phys = 0x00000000UL, > - .size = 0x20000000UL, > + .size = 0x40000000UL, > .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > PTE_BLOCK_NON_SHARE | > PTE_BLOCK_PXN | PTE_BLOCK_UXN > -- > 2.48.1 > -- Ansuel