From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alexandre Ghiti Date: Thu, 18 Jul 2024 18:45:00 +0200 Subject: [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries In-Reply-To: <20240712083850.4242-3-yongxuan.wang@sifive.com> References: <20240712083850.4242-1-yongxuan.wang@sifive.com> <20240712083850.4242-3-yongxuan.wang@sifive.com> Message-ID: <6908e437-bf1c-4fae-bb34-b5c30dae97ff@ghiti.fr> List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On 12/07/2024 10:38, Yong-Xuan Wang wrote: > Add entries for the Svade and Svadu extensions to the riscv,isa-extensions > property. > > Signed-off-by: Yong-Xuan Wang > --- > .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 468c646247aa..e91a6f4ede38 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -153,6 +153,34 @@ properties: > ratified at commit 3f9ed34 ("Add ability to manually trigger > workflow. (#2)") of riscv-time-compare. > > + - const: svade > + description: | > + The standard Svade supervisor-level extension for SW-managed PTE A/D > + bit updates as ratified in the 20240213 version of the privileged > + ISA specification. > + > + Both Svade and Svadu extensions control the hardware behavior when > + the PTE A/D bits need to be set. The default behavior for the four > + possible combinations of these extensions in the device tree are: > + 1) Neither Svade nor Svadu present in DT => It is technically > + unknown whether the platform uses Svade or Svadu. Supervisor > + software should be prepared to handle either hardware updating > + of the PTE A/D bits or page faults when they need updated. > + 2) Only Svade present in DT => Supervisor must assume Svade to be > + always enabled. > + 3) Only Svadu present in DT => Supervisor must assume Svadu to be > + always enabled. > + 4) Both Svade and Svadu present in DT => Supervisor must assume > + Svadu turned-off at boot time. To use Svadu, supervisor must > + explicitly enable it using the SBI FWFT extension. > + > + - const: svadu > + description: | > + The standard Svadu supervisor-level extension for hardware updating > + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request > + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade > + dt-binding description for more details. > + > - const: svinval > description: > The standard Svinval supervisor-level extension for fine-grained Reviewed-by: Alexandre Ghiti Thanks, Alex From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6E616C3DA49 for ; Thu, 18 Jul 2024 16:45:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=pdoMaK0f+qK0vD6wm93elc0vqZ/yuGUwz+ky2k9U114=; b=hs33C6WPN+EjqH RwghtYsB90tDmTvZrGGhMgzNFU2jPAewu2uwLNvC3ajs2NYcd/0dcMmN0lu8ALMaUGLfwytnokf0n WFxAFCg+5Je/w5Syc+eiCEO+NsXQOPXqlUXKxSnU4X4FctsyInFxNy3z5QmLAlBaApPplMlJ/5Zos mmsDiH943QsFlPLjGkVpZA21Jucz86kurY56CYYXbtYs+py59+fNm1dD3UAJTk1oZv4gPhYCglIsR Z8v3PZf4xrl9iiw/KDf7GzvyCWcZ2eBy1gqSBMeQemvlQIGdInB5OMuQZjoaPI6daoUxLANu0ox9+ 4S+bHNH9GiJFrIezhZrg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sUUFm-000000000lT-0mBb; Thu, 18 Jul 2024 16:45:14 +0000 Received: from relay9-d.mail.gandi.net ([217.70.183.199]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sUUFh-000000000kb-2ZJ9; Thu, 18 Jul 2024 16:45:12 +0000 Received: by mail.gandi.net (Postfix) with ESMTPSA id C9676FF808; Thu, 18 Jul 2024 16:45:00 +0000 (UTC) Message-ID: <6908e437-bf1c-4fae-bb34-b5c30dae97ff@ghiti.fr> Date: Thu, 18 Jul 2024 18:45:00 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries Content-Language: en-US To: Yong-Xuan Wang , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , devicetree@vger.kernel.org References: <20240712083850.4242-1-yongxuan.wang@sifive.com> <20240712083850.4242-3-yongxuan.wang@sifive.com> From: Alexandre Ghiti In-Reply-To: <20240712083850.4242-3-yongxuan.wang@sifive.com> X-GND-Sasl: alex@ghiti.fr X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240718_094511_094694_2DBE7982 X-CRM114-Status: GOOD ( 16.63 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On 12/07/2024 10:38, Yong-Xuan Wang wrote: > Add entries for the Svade and Svadu extensions to the riscv,isa-extensions > property. > > Signed-off-by: Yong-Xuan Wang > --- > .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 468c646247aa..e91a6f4ede38 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -153,6 +153,34 @@ properties: > ratified at commit 3f9ed34 ("Add ability to manually trigger > workflow. (#2)") of riscv-time-compare. > > + - const: svade > + description: | > + The standard Svade supervisor-level extension for SW-managed PTE A/D > + bit updates as ratified in the 20240213 version of the privileged > + ISA specification. > + > + Both Svade and Svadu extensions control the hardware behavior when > + the PTE A/D bits need to be set. The default behavior for the four > + possible combinations of these extensions in the device tree are: > + 1) Neither Svade nor Svadu present in DT => It is technically > + unknown whether the platform uses Svade or Svadu. Supervisor > + software should be prepared to handle either hardware updating > + of the PTE A/D bits or page faults when they need updated. > + 2) Only Svade present in DT => Supervisor must assume Svade to be > + always enabled. > + 3) Only Svadu present in DT => Supervisor must assume Svadu to be > + always enabled. > + 4) Both Svade and Svadu present in DT => Supervisor must assume > + Svadu turned-off at boot time. To use Svadu, supervisor must > + explicitly enable it using the SBI FWFT extension. > + > + - const: svadu > + description: | > + The standard Svadu supervisor-level extension for hardware updating > + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request > + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade > + dt-binding description for more details. > + > - const: svinval > description: > The standard Svinval supervisor-level extension for fine-grained Reviewed-by: Alexandre Ghiti Thanks, Alex _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE48714372D; Thu, 18 Jul 2024 16:45:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.199 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721321110; cv=none; b=sz2vBcYmPqGDVMNj+gUU7xEmE2iCEeXU0PfArjS76A5GooyBD1bzbTFmQc6qRXiu8r6TzKLz9dCC9qApiPzv4F1r6KqaYsc2ZukkP6uUUnQ3rvd3TjlSm+aeK2Ssgtngw+KYmIcTgWeg5JgafThkiO+gcJVaihimz7HCdy6HJh4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721321110; c=relaxed/simple; bh=ho4kXrb83dG7s2zTkRmierlLx/1L8Hdnc7xDarwrA6Y=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=rzM2HLH+sKV/X2esjVgIO/pk6uOqFfuXJL6gLLxW2fGBsrIP6+KTfAXP+0YB22KxrupqK4FloIP+JnzmJ6jc3SL/BFz2O2V/nOZ4Ly1wMIO8R6Tkgxr0oTdkOsPHtQnlKtsd9VeHj1Q2lm1LTm5Rh0EB2HGhIWUMtCvJmQcyZSk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ghiti.fr; spf=pass smtp.mailfrom=ghiti.fr; arc=none smtp.client-ip=217.70.183.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ghiti.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ghiti.fr Received: by mail.gandi.net (Postfix) with ESMTPSA id C9676FF808; Thu, 18 Jul 2024 16:45:00 +0000 (UTC) Message-ID: <6908e437-bf1c-4fae-bb34-b5c30dae97ff@ghiti.fr> Date: Thu, 18 Jul 2024 18:45:00 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries Content-Language: en-US To: Yong-Xuan Wang , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org Cc: greentime.hu@sifive.com, vincent.chen@sifive.com, Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , devicetree@vger.kernel.org References: <20240712083850.4242-1-yongxuan.wang@sifive.com> <20240712083850.4242-3-yongxuan.wang@sifive.com> From: Alexandre Ghiti In-Reply-To: <20240712083850.4242-3-yongxuan.wang@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-GND-Sasl: alex@ghiti.fr On 12/07/2024 10:38, Yong-Xuan Wang wrote: > Add entries for the Svade and Svadu extensions to the riscv,isa-extensions > property. > > Signed-off-by: Yong-Xuan Wang > --- > .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 468c646247aa..e91a6f4ede38 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -153,6 +153,34 @@ properties: > ratified at commit 3f9ed34 ("Add ability to manually trigger > workflow. (#2)") of riscv-time-compare. > > + - const: svade > + description: | > + The standard Svade supervisor-level extension for SW-managed PTE A/D > + bit updates as ratified in the 20240213 version of the privileged > + ISA specification. > + > + Both Svade and Svadu extensions control the hardware behavior when > + the PTE A/D bits need to be set. The default behavior for the four > + possible combinations of these extensions in the device tree are: > + 1) Neither Svade nor Svadu present in DT => It is technically > + unknown whether the platform uses Svade or Svadu. Supervisor > + software should be prepared to handle either hardware updating > + of the PTE A/D bits or page faults when they need updated. > + 2) Only Svade present in DT => Supervisor must assume Svade to be > + always enabled. > + 3) Only Svadu present in DT => Supervisor must assume Svadu to be > + always enabled. > + 4) Both Svade and Svadu present in DT => Supervisor must assume > + Svadu turned-off at boot time. To use Svadu, supervisor must > + explicitly enable it using the SBI FWFT extension. > + > + - const: svadu > + description: | > + The standard Svadu supervisor-level extension for hardware updating > + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request > + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade > + dt-binding description for more details. > + > - const: svinval > description: > The standard Svinval supervisor-level extension for fine-grained Reviewed-by: Alexandre Ghiti Thanks, Alex