Re: [PATCH 7/9] drm/i915/display: psr enable DC3CO support

[Jani Nikula <jani.nikula@linux.intel.com>]

On Tue, 09 Dec 2025, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
> if DC3CO allowed and psr2 is enabled, update dc3co_source

Yeah, I can read the code, but what does it mean? Why?

>
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 9c616f449ad6..d4c5dc6dcc82 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -3007,6 +3007,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
>  		if (crtc_state->crc_enabled && psr->enabled)
>  			intel_psr_force_update(intel_dp);
>  
> +		if (psr->enabled &&
> +		    psr->sel_update_enabled &&
> +		    intel_dc3co_allowed(display)) {
> +			intel_dc3co_source_set(display, DC3CO_SOURCE_PSR2);
> +		}
> +
>  		/*
>  		 * Clear possible busy bits in case we have
>  		 * invalidate -> flip -> flush sequence.

-- 
Jani Nikula, Intel