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Date: Mon, 14 Nov 2022 20:00:44 +0800
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Cc: baolu.lu@linux.intel.com
Subject: Re: [PATCH] iommu/vt-d: Set SRE bit when hardware has SRS cap
To: Tina Zhang <tina.zhang@intel.com>, iommu@lists.linux.dev
References: <20221114085514.1105039-1-tina.zhang@intel.com>
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From: Baolu Lu <baolu.lu@linux.intel.com>
In-Reply-To: <20221114085514.1105039-1-tina.zhang@intel.com>
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On 2022/11/14 16:55, Tina Zhang wrote:
> SRS cap is the hardware cap telling if the hardware IOMMU can support
> requests seeking supervisor privilege or not. SRE bit in scalable-mode
> PASID table entry is treated as Reserved(0) for implementation not
> supporting SRS cap.
> 
> Checking SRS cap before setting SRE bit can avoid the non-recoverable
> fault of "Non-zero reserved field set in PASID Table Entry" caused by
> setting SRE bit while there is no SRS cap support.
> 
> Currently, both intel_pasid_setup_first_level() and
> intel_pasid_setup_second_level() implicitly take care about of it. The
> only missing SRS cap checking is in intel_pasid_setup_pass_through().
> 
> Fixes: 6f7db75e1c46 ("iommu/vt-d: Add second level page table interface")
> Signed-off-by: Tina Zhang<tina.zhang@intel.com>

Nice catch! Tina.

Can you please double check  intel_pasid_setup_second_level()? Its seems
that we missed such check there as well.

Best regards,
baolu