Re: [PATCH v7 08/11] cxl: Coordinate sibling functions for CXL reset

["Dan Williams (nvidia)" <djbw@kernel.org>]

Srirangan Madhavan wrote:
> CXL Device Reset affects all CXL.cache and CXL.mem functions in the reset
> scope. Lock same-scope siblings with pci_dev_trylock(), save/disable them,
> drain pending transactions, and hold IOMMU reset blocks until recovery.
> 
> Also include mem-capable siblings in HDM range validation and CPU cache
> invalidation. Cache-only siblings are quiesced, but skipped for HDM range
> handling.

PCI reset locking and ordering is already a source of some burden
without adding this new sibling model to consider.

Is there evidence that multi-function CXL devices, where most of the
functions are non-CXL, is going to be a common occurrence?

In other words if CXL reset borrowed the bus reset locking model:

    if (pci_bus_trylock(bus)) {
        pci_bus_save_and_disable_locked(bus);
        might_sleep();
	rc = cxl_request_and_flush_hdm(bus);
	if (rc == 0) {
		rc = cxl_reset_execute(pdev);
		cxl_release_and_flush_hdm(bus);
	}
        pci_bus_restore_locked(bus);
        pci_bus_unlock(bus);
    }

The cost is disturbing some non-CXL functions, the benefit is reusing an
existing reset order / locking model.