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Tue, 12 Mar 2024 13:39:39 +0000 (GMT) Message-ID: <6ab6a17b-dc2a-4d98-81f0-0e45b412516d@linux.ibm.com> Date: Tue, 12 Mar 2024 19:09:32 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 07/10] ppc/pnv: Permit ibm, pa-features set per machine variant Content-Language: en-US To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, Daniel Henrique Barboza , David Gibson References: <20240312131419.2196845-1-npiggin@gmail.com> <20240312131419.2196845-8-npiggin@gmail.com> From: Harsh Prateek Bora In-Reply-To: <20240312131419.2196845-8-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: i0cDuYAltb-1cmjSG5o0iocK4TcQw1yq X-Proofpoint-GUID: 0YONbxTSIecfq1pfPLeSMdPh74kX4v57 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-12_08,2024-03-12_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 bulkscore=0 mlxlogscore=999 spamscore=0 suspectscore=0 clxscore=1015 phishscore=0 adultscore=0 mlxscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311290000 definitions=main-2403120105 Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/12/24 18:44, Nicholas Piggin wrote: > This allows different pa-features for powernv8/9/10. > > Signed-off-by: Nicholas Piggin Reviewed-by: Harsh Prateek Bora > --- > hw/ppc/pnv.c | 41 +++++++++++++++++++++++++++++------------ > 1 file changed, 29 insertions(+), 12 deletions(-) > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index aa9786e970..52d964f77a 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -133,7 +133,7 @@ static int get_cpus_node(void *fdt) > * device tree, used in XSCOM to address cores and in interrupt > * servers. > */ > -static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) > +static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) > { > PowerPCCPU *cpu = pc->threads[0]; > CPUState *cs = CPU(cpu); > @@ -149,11 +149,6 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) > uint32_t cpufreq = 1000000000; > uint32_t page_sizes_prop[64]; > size_t page_sizes_prop_size; > - const uint8_t pa_features[] = { 24, 0, > - 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, > - 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, > - 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, > - 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; > int offset; > char *nodename; > int cpus_offset = get_cpus_node(fdt); > @@ -236,15 +231,14 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) > page_sizes_prop, page_sizes_prop_size))); > } > > - _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", > - pa_features, sizeof(pa_features)))); > - > /* Build interrupt servers properties */ > for (i = 0; i < smt_threads; i++) { > servers_prop[i] = cpu_to_be32(pc->pir + i); > } > _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", > servers_prop, sizeof(*servers_prop) * smt_threads))); > + > + return offset; > } > > static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, > @@ -299,6 +293,17 @@ PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) > return chip; > } > > +/* > + * Same as spapr pa_features_207 except pnv always enables CI largepages bit. > + * HTM is always enabled because TCG does implement HTM, it's just a > + * degenerate implementation. > + */ > +static const uint8_t pa_features_207[] = { 24, 0, > + 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, > + 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, > + 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; > + > static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) > { > static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; > @@ -311,8 +316,12 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) > > for (i = 0; i < chip->nr_cores; i++) { > PnvCore *pnv_core = chip->cores[i]; > + int offset; > + > + offset = pnv_dt_core(chip, pnv_core, fdt); > > - pnv_dt_core(chip, pnv_core, fdt); > + _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", > + pa_features_207, sizeof(pa_features_207)))); > > /* Interrupt Control Presenters (ICP). One per core. */ > pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); > @@ -335,8 +344,12 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) > > for (i = 0; i < chip->nr_cores; i++) { > PnvCore *pnv_core = chip->cores[i]; > + int offset; > > - pnv_dt_core(chip, pnv_core, fdt); > + offset = pnv_dt_core(chip, pnv_core, fdt); > + > + _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", > + pa_features_207, sizeof(pa_features_207)))); > } > > if (chip->ram_size) { > @@ -358,8 +371,12 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) > > for (i = 0; i < chip->nr_cores; i++) { > PnvCore *pnv_core = chip->cores[i]; > + int offset; > + > + offset = pnv_dt_core(chip, pnv_core, fdt); > > - pnv_dt_core(chip, pnv_core, fdt); > + _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", > + pa_features_207, sizeof(pa_features_207)))); > } > > if (chip->ram_size) {