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From: Jan Beulich <jbeulich@suse.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: "Roger Pau Monné" <roger.pau@citrix.com>,
	"Jason Andryuk" <jason.andryuk@amd.com>,
	"Teddy Astie" <teddy.astie@vates.tech>,
	"Ross Lagerwall" <ross.lagerwall@citrix.com>,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 1/6] nestedsvm: Fix CR3 MBZ check
Date: Thu, 25 Jun 2026 13:58:46 +0200	[thread overview]
Message-ID: <6b4564ff-49b4-4332-b2ac-5ae093b62de1@suse.com> (raw)
In-Reply-To: <b9ddc37c-216b-4c18-8d77-03ce641d2614@citrix.com>

On 26.05.2026 15:01, Andrew Cooper wrote:
> On 26/05/2026 1:40 pm, Ross Lagerwall wrote:
>> The existing code checks for any reserved bit set while the APM only
>> considers it invalid if an MBZ bit is set. Relax the check to match the
>> APM and hardware.
>>
>> Some of the reserved bits were observed to be set running Rocky Linux
>> 10.1 on Xen on Xen.
>>
>> Fixes: 9a779e4fc161 ("Implement SVM specific part for Nested Virtualization")
>> Signed-off-by: Ross Lagerwall <ross.lagerwall@citrix.com>
>> ---
>>  xen/arch/x86/hvm/svm/vmcb.c | 6 ++----
>>  1 file changed, 2 insertions(+), 4 deletions(-)
>>
>> diff --git a/xen/arch/x86/hvm/svm/vmcb.c b/xen/arch/x86/hvm/svm/vmcb.c
>> index 975a1eaef806..9ada491e57db 100644
>> --- a/xen/arch/x86/hvm/svm/vmcb.c
>> +++ b/xen/arch/x86/hvm/svm/vmcb.c
>> @@ -347,10 +347,8 @@ bool svm_vmcb_isvalid(
>>          PRINTF("CR0: bits [63:32] are not zero (%#"PRIx64")\n", cr0);
>>  
>>      if ( (cr0 & X86_CR0_PG) &&
>> -         ((cr3 & 7) ||
>> -          ((!(cr4 & X86_CR4_PAE) || (efer & EFER_LMA)) && (cr3 & 0xfe0)) ||
>> -          ((efer & EFER_LMA) &&
>> -           (cr3 >> v->domain->arch.cpuid->extd.maxphysaddr))) )
>> +         ((efer & EFER_LMA) &&
>> +           (cr3 >> v->domain->arch.cpuid->extd.maxphysaddr)) )
>>          PRINTF("CR3: MBZ bits are set (%#"PRIx64")\n", cr3);
>>  
>>      valid = hvm_cr4_guest_valid_bits(v->domain);
> 
> The APM does say MBZ for VMRUN, but the end result of a VMEntry (virtual
> or otherwise) must be a legal CR3 value.
> 
> For 5.2.1 CR3 Register (Legacy) and 5.3.2 CR3 (Long), the APM states:
> 
> Reserved Bits. Reserved fields should be cleared to 0 by software when
> writing CR3.
> 
> What's the real behaviour for trying to set a reserved, non-MBZ bit in
> CR3?  On Intel it's strictly a #GP, and I really hope it's the same on AMD.

As to Intel - are you sure? The MOV to/from control register page has this:
"When PCIDs are not enabled, bits 2:0 and bits 11:5 of CR3 are not used and
attempts to set them are ignored."

Jan


  parent reply	other threads:[~2026-06-25 11:59 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-26 12:40 [PATCH v1 0/6] nestedsvm: Misc fixes Ross Lagerwall
2026-05-26 12:40 ` [PATCH v1 1/6] nestedsvm: Fix CR3 MBZ check Ross Lagerwall
2026-05-26 13:01   ` Andrew Cooper
2026-05-26 13:23     ` Ross Lagerwall
2026-08-06 10:43       ` Ross Lagerwall
2026-06-25 11:58     ` Jan Beulich [this message]
2026-05-26 12:40 ` [PATCH v1 2/6] nestedsvm: Adjust L2's DR intercept when adjusting L1 Ross Lagerwall
2026-05-26 13:45   ` Andrew Cooper
2026-05-26 12:40 ` [PATCH v1 3/6] nestedsvm: Use the correct VMCB for vGIF Ross Lagerwall
2026-05-26 12:40 ` [PATCH v1 4/6] nestedsvm: Set GIF during VMRUN if vGIF is enabled Ross Lagerwall
2026-05-26 12:40 ` [PATCH v1 5/6] nestedsvm: Fix deferred event injection Ross Lagerwall
2026-09-11 10:56   ` Andrew Cooper
2026-09-11 13:37     ` Ross Lagerwall
2026-05-26 12:40 ` [PATCH v1 6/6] nestedsvm: Allow destroying the domain fully Ross Lagerwall
2026-06-25 12:11   ` Jan Beulich
2026-08-06 10:46 ` [PATCH v1 0/6] nestedsvm: Misc fixes Ross Lagerwall

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