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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-61500491d12sm4326817a12.11.2025.07.29.01.23.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Jul 2025 01:23:18 -0700 (PDT) Message-ID: <6b903628-9abf-4b9e-971e-e9338308d693@oss.qualcomm.com> Date: Tue, 29 Jul 2025 10:23:13 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 24/24] arm64: dts: qcom: x1e80100: Describe GPU_CC power plumbing requirements To: Stephan Gerhold Cc: Konrad Dybcio , Ulf Hansson , Johan Hovold , Bjorn Andersson , Taniya Das , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Imran Shaik , Bartosz Golaszewski , Dmitry Baryshkov , cros-qcom-dts-watchers@chromium.org, Douglas Anderson , Vinod Koul , Richard Acayan , Ajit Pandey , Luca Weiss , Jonathan Marek , Neil Armstrong , Jagadeesh Kona , Akhil P Oommen , Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski References: <20250728-topic-gpucc_power_plumbing-v1-0-09c2480fe3e6@oss.qualcomm.com> <20250728-topic-gpucc_power_plumbing-v1-24-09c2480fe3e6@oss.qualcomm.com> <50868cd8-68a9-4bad-99f3-8cf542886fb6@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=JovxrN4C c=1 sm=1 tr=0 ts=688884fa cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=npIohlpTwfGSXeC_WVoA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-ORIG-GUID: VJZXq1_fAnXuCGuJ-meS7Az6R0qFk1kf X-Proofpoint-GUID: VJZXq1_fAnXuCGuJ-meS7Az6R0qFk1kf X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzI5MDA2MiBTYWx0ZWRfX+iEiEYwN9I6H +YloMVYA5LiNsQN7H8SzfgBTRno6nTe/9o42hLM6GV7y9wFXEi1/R03OOgiLx7azzMzWe6rjdWE rLSdmd4oNkLY2ZOuyo9BsZqhdK6KLKoTqI9+/uDWMNHPWQvsQYlKxi40rAEeNMTVckQBDeLr/CV llIYuy6zU9U9fe7avwGWjmkybQD1dihMWayikNs5ZuMsFrJYopldFzISNW2AFj3Ju+1Abloze1A CZnbp2i8zQWAhz0WzmBi2dlnWnbLlAhluw7K2ugrTa8rwLMVzOReYSG/UlK4UOmLhO4qT0Bfabm A9uvgJ8BIkU2FIqGITs6nb+iZ5qjQB0c40vq3FjZ+jcoa3F4SEOIEC1DHhul5CUA0xhy9uEWrSB Bp+iKw4c2IkBf0J7Ue4xvo2SSipi3FZ29zSTq7sB1XjdomH5sc2/Abiqy7ruTKBH/SESwCiR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-29_02,2025-07-28_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 priorityscore=1501 bulkscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 spamscore=0 mlxlogscore=999 mlxscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507290062 On 7/29/25 8:34 AM, Stephan Gerhold wrote: > On Mon, Jul 28, 2025 at 11:31:10PM +0200, Konrad Dybcio wrote: >> On 7/28/25 7:10 PM, Stephan Gerhold wrote: >>> On Mon, Jul 28, 2025 at 06:16:24PM +0200, Konrad Dybcio wrote: >>>> From: Konrad Dybcio >>>> >>>> A number of power rails must be powered on in order for GPU_CC to >>>> function. Ensure that's conveyed to the OS. >>>> >>>> Fixes: 721e38301b79 ("arm64: dts: qcom: x1e80100: Add gpu support") >>>> Signed-off-by: Konrad Dybcio >>>> --- >>>> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 6 ++++++ >>>> 1 file changed, 6 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>>> index 5e9a8fa3cf96468b12775f91192cbd779d5ce946..6620517fbb0f3ed715c4901ec53dcbc6235be88f 100644 >>>> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >>>> @@ -3928,6 +3928,12 @@ gpucc: clock-controller@3d90000 { >>>> clocks = <&bi_tcxo_div2>, >>>> <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>, >>>> <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>; >>>> + >>>> + power-domains = <&rpmhpd RPMHPD_CX>, >>>> + <&rpmhpd RPMHPD_MX>, >>>> + <&rpmhpd RPMHPD_GFX>, >>>> + <&rpmhpd RPMHPD_GMXC>; >>>> + >>>> #clock-cells = <1>; >>>> #reset-cells = <1>; >>>> #power-domain-cells = <1>; >>>> >>> >>> To repeat your own message from a couple of months back [1]: >>> >>>> You shouldn't be messing with VDD_GFX on platforms with a GMU. >>>> >>>> Parts of the clock controller are backed by one of the MX rails, >>>> with some logic depending on CX/GFX, but handling of the latter is >>>> fully deferred to the GMU firmware. >>>> >>>> Konrad >>> >>> Please describe somewhere in the cover letter or the individual patches >>> how this relates to the responsibilities of the GMU. I searched for >>> "GMU" in the patch series and couldn't find any note about this. >>> >>> Also: How much is a plain "power on" votes (without a corresponding >>> "required-opps") really worth nowadays? An arbitrary low voltage level >>> on those rails won't be sufficient to make the GPU_CC actually >>> "function". Do you need "required-opps" here? In the videocc/camcc case >>> we have those. >> >> Right, I failed to capture this. >> >> The GFX rail should be powered on before unclamping the GX_GDSC (as >> per the programming guide). The clock controller HPG however doesn't >> seem to have a concept of RPMh, so it says something that amounts to >> "tell the PMIC to supply power on this rail". In Linux, since Commit >> e3e56c050ab6 ("soc: qcom: rpmhpd: Make power_on actually enable the >> domain") we don't really need a defined level for this (perhaps it's >> more ""portable"" across potential fuse-bins if we don't hardcode the >> lowest level anyway?). > > Thanks, I forgot that we have this commit. > >> >> However after that happens, the level scaling is done by the GMU >> firmware. This holds for allOf CX/MX/GFX. I'm not super sure if >> both MX and (G)MXC need to both be captured together - downstream >> seems to describe MXC as a child of MX (in socname-regulators.dtsi), >> but I'm not really sure this is true in hardware. >> >> The GPU driver currently first enables the GX_GDSC and only then >> does it kickstart the GMU firmware. Downstream seems to do that as >> well. So on a second thought, since we've not seen any errors so >> far, it calls into question what role the GFX rail plays in the >> GX_GDSC's powering up.. >> > > It might play a role, but we wouldn't know since AFAICT we don't support > enabling the GX_GDSC. Look at the beautiful gdsc_gx_do_nothing_enable() > function, it basically just defers the entire task to the GMU. The GDSC > just exists in Linux so we can turn it *off* during GMU crashes. :D OHHHHH snap! I, on the other hand, forgot we have *that* commit.. > I think we should identify precisely which votes we are missing, instead > of making blanket votes for all the power rails somehow related to the > GPU. In this case this means: Which rails do we need to vote for to make > the GMU turn on? If there are no votes necessary after the GMU is on, > it's better to have none IMO. The GMU pokes at RPMh directly (see a6xx_hfi.c), so we indeed just need to make sure that it can turn on.. Which in short means the *C*X_GDSC must be able to power up, which doesn't have any special requirements. The only question that's left is basically whether MX_C must be on. I'll try testing that in practice. Konrad