From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Rayhan Faizel <rayhan.faizel@gmail.com>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: Re: [PATCH 1/3] hw/nvram: Add BCM2835 OTP device
Date: Mon, 13 May 2024 15:30:14 +0200 [thread overview]
Message-ID: <6bb04e15-5bfd-4ac6-98a1-33c65a6f1663@linaro.org> (raw)
In-Reply-To: <20240510141010.656561-2-rayhan.faizel@gmail.com>
Hi Rayhan,
On 10/5/24 16:10, Rayhan Faizel wrote:
> The OTP device registers are currently stubbed. For now, the device
> houses the OTP rows which will be accessed directly by other peripherals.
>
> Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
> ---
> hw/nvram/bcm2835_otp.c | 187 +++++++++++++++++++++++++++++++++
> hw/nvram/meson.build | 1 +
> include/hw/nvram/bcm2835_otp.h | 43 ++++++++
> 3 files changed, 231 insertions(+)
> create mode 100644 hw/nvram/bcm2835_otp.c
> create mode 100644 include/hw/nvram/bcm2835_otp.h
> +static void bcm2835_otp_write(void *opaque, hwaddr addr,
> + uint64_t value, unsigned int size)
> +{
> + switch (addr) {
> + case BCM2835_OTP_BOOTMODE_REG:
> + qemu_log_mask(LOG_UNIMP,
> + "bcm2835_otp: BCM2835_OTP_BOOTMODE_REG\n");
> + break;
> + case BCM2835_OTP_CONFIG_REG:
> + qemu_log_mask(LOG_UNIMP,
> + "bcm2835_otp: BCM2835_OTP_CONFIG_REG\n");
> + break;
> + case BCM2835_OTP_CTRL_LO_REG:
> + qemu_log_mask(LOG_UNIMP,
> + "bcm2835_otp: BCM2835_OTP_CTRL_LO_REG\n");
> + break;
> + case BCM2835_OTP_CTRL_HI_REG:
> + qemu_log_mask(LOG_UNIMP,
> + "bcm2835_otp: BCM2835_OTP_CTRL_HI_REG\n");
> + break;
> + case BCM2835_OTP_STATUS_REG:
> + qemu_log_mask(LOG_UNIMP,
> + "bcm2835_otp: BCM2835_OTP_STATUS_REG\n");
> + break;
> + case BCM2835_OTP_BITSEL_REG:
> + qemu_log_mask(LOG_UNIMP,
> + "bcm2835_otp: BCM2835_OTP_BITSEL_REG\n");
> + break;
> + case BCM2835_OTP_DATA_REG:
> + qemu_log_mask(LOG_UNIMP,
> + "bcm2835_otp: BCM2835_OTP_DATA_REG\n");
> + break;
> + case BCM2835_OTP_ADDR_REG:
> + qemu_log_mask(LOG_UNIMP,
> + "bcm2835_otp: BCM2835_OTP_ADDR_REG\n");
> + break;
> + case BCM2835_OTP_WRITE_DATA_READ_REG:
> + qemu_log_mask(LOG_UNIMP,
> + "bcm2835_otp: BCM2835_OTP_WRITE_DATA_READ_REG\n");
> + break;
> + case BCM2835_OTP_INIT_STATUS_REG:
> + qemu_log_mask(LOG_UNIMP,
> + "bcm2835_otp: BCM2835_OTP_INIT_STATUS_REG\n");
> + break;
> + default:
> + qemu_log_mask(LOG_GUEST_ERROR,
> + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
> + }
> +}
> +
> +static const MemoryRegionOps bcm2835_otp_ops = {
> + .read = bcm2835_otp_read,
> + .write = bcm2835_otp_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
s/valid/impl/ here, this is your implementation. It isn't illegal to
access these registers with a non 32-bit size.
> + .min_access_size = 4,
> + .max_access_size = 4,
> + },
> +};
> +/* https://elinux.org/BCM2835_registers#OTP */
> +#define BCM2835_OTP_BOOTMODE_REG 0x00
> +#define BCM2835_OTP_CONFIG_REG 0x04
> +#define BCM2835_OTP_CTRL_LO_REG 0x08
> +#define BCM2835_OTP_CTRL_HI_REG 0x0c
> +#define BCM2835_OTP_STATUS_REG 0x10
> +#define BCM2835_OTP_BITSEL_REG 0x14
> +#define BCM2835_OTP_DATA_REG 0x18
> +#define BCM2835_OTP_ADDR_REG 0x1c
> +#define BCM2835_OTP_WRITE_DATA_READ_REG 0x20
> +#define BCM2835_OTP_INIT_STATUS_REG 0x24
next prev parent reply other threads:[~2024-05-13 13:30 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-10 14:10 [PATCH 0/3] Initial support for One-Time Programmable Memory (OTP) in BCM2835 Rayhan Faizel
2024-05-10 14:10 ` [PATCH 1/3] hw/nvram: Add BCM2835 OTP device Rayhan Faizel
2024-05-13 13:30 ` Philippe Mathieu-Daudé [this message]
2024-05-13 13:49 ` Philippe Mathieu-Daudé
2024-05-10 14:10 ` [PATCH 2/3] hw/arm: Connect OTP device to BCM2835 Rayhan Faizel
2024-05-13 13:41 ` Philippe Mathieu-Daudé
2024-05-10 14:10 ` [PATCH 3/3] hw/misc: Implement mailbox properties for customer OTP and device specific private keys Rayhan Faizel
2024-05-13 13:51 ` Philippe Mathieu-Daudé
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