From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 1/3] drm/i915: extract gmbus_wait_hw_status Date: Wed, 05 Sep 2012 22:25:03 +0100 Message-ID: <6c3329$5sb1j3@orsmga002.jf.intel.com> References: <1346873081-1305-1-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id E56769E752 for ; Wed, 5 Sep 2012 14:25:09 -0700 (PDT) In-Reply-To: <1346873081-1305-1-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Wed, 5 Sep 2012 21:24:39 +0200, Daniel Vetter wrote: > The gmbus interrupt generation is rather fiddly: We can only ever > enable one interrupt source (but we always want to check for NAK > in addition to the real bit). And the bits in the gmbus status > register don't map at all to the bis in the irq register. > > To prepare for this mess, start by extracting the hw status wait > loop into it's own function, consolidate the NAK error handling a > bit. To keep things flexible, pass in the status bit we care about > (in addition to any NAK signalling). There are some subtle changes in that we introduce new error detection which is promptly ignored with a different wait period, but the changes look good. Reviewed-by: Chris Wilson -- Chris Wilson, Intel Open Source Technology Centre