From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 3/3] drm/i915: use the gmbus irq for waits Date: Wed, 05 Sep 2012 22:34:54 +0100 Message-ID: <6c3329$5sb84q@orsmga002.jf.intel.com> References: <1346873081-1305-1-git-send-email-daniel.vetter@ffwll.ch> <1346873081-1305-3-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 3FA589E752 for ; Wed, 5 Sep 2012 14:34:59 -0700 (PDT) In-Reply-To: <1346873081-1305-3-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter List-Id: intel-gfx@lists.freedesktop.org On Wed, 5 Sep 2012 21:24:41 +0200, Daniel Vetter wrote: > We need two special things to properly wire this up: > - Add another argument to gmbus_wait_hw_status to pass in the > correct interrupt bit in gmbus4. > - Since we can only get an irq for one of the two events we want, > hand-roll the wait_event_timeout code so that we wake up every > jiffie and can check for NAKs. This way we also subsume gmbus > support for platforms without interrupts (or where those are not > yet enabled). > > The important bit really is to only enable one gmbus interrupt source > at the same time - with that piece of lore figured out, this seems to > work flawlessly. Outline looks good. Did have a worry over the conversion to schedule(1), but then realised that is equivalent to the current msleep. So there is a potential that we need to do better for gen2/3. Need to dig a little more, so just a-b for now. -Chris -- Chris Wilson, Intel Open Source Technology Centre