From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 2/3] drm/i915: wire up gmbus irq handler Date: Wed, 05 Sep 2012 22:52:21 +0100 Message-ID: <6c3329$5sbht6@orsmga002.jf.intel.com> References: <1346873081-1305-1-git-send-email-daniel.vetter@ffwll.ch> <1346873081-1305-2-git-send-email-daniel.vetter@ffwll.ch> <453bf0$5kg1cv@azsmga001.ch.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 3D965A02D9 for ; Wed, 5 Sep 2012 14:52:26 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Wed, 5 Sep 2012 23:36:46 +0200, Daniel Vetter wrote: > On Wed, Sep 5, 2012 at 11:29 PM, Chris Wilson wrote: > > On Wed, 5 Sep 2012 21:24:40 +0200, Daniel Vetter wrote: > >> Only enables the interrupt and puts a irq handler into place, doesn't > >> do anything yet. > >> > >> Unfortunately there's no gmbus interrupt support for gen2/3 (safe for > >> pnv, but there the irq is marked as "Test mode"). > > > > The basics look good, but the paranoia says I'd like for the interrupt > > to only be enabled as required. > > I do that ;-) The real interrupt generation is also controlled by > GMBUS4 - as long as that's 0, no interrupt shows up anywhere. And > frobbing GMBUS4 is much easier than adding a bunch of of spinlocks > around frobbing SDE_IIR ... Indeed, killing it at source is preferrable all round. Are you sure GMBUS4 is always initialised to zero? So this patch looks sound, Reviewed-by: Chris Wilson -Chris -- Chris Wilson, Intel Open Source Technology Centre