From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 3/3] drm/i915: fix FDI lane calculation Date: Thu, 29 Nov 2012 13:59:55 +0000 Message-ID: <6c3329$7dllih@orsmga002.jf.intel.com> References: <1354195773-4022-1-git-send-email-przanoni@gmail.com> <1354195773-4022-3-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 94940E640D for ; Thu, 29 Nov 2012 06:00:03 -0800 (PST) In-Reply-To: <1354195773-4022-3-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni , intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Thu, 29 Nov 2012 11:29:33 -0200, Paulo Zanoni wrote: > From: Paulo Zanoni > > The previous code was making the bps value 5% higher than what the > spec says, which was enough to make certain VGA modes require 3 lanes > instead of 2, which makes us reject these modes on Haswell since it > only has 2 FDI lanes. For previous gens this was not much of a > problem, since they had 4 lanes, and requiring more lanes than the > needed is ok, as long as you have all the lanes. > > Notice that this might improve the case where we use pipes B and C on > Ivy Bridge since both pipes only have 4 lanes to share (see > ironlake_check_fdi_lanes). > > Cc: Adam Jackson > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_display.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > As it is, this one will make the list of supported modes on Haswell VGA bigger, > so we could skip 3.8 and send this through 3.9, so we have plently of time to > get confident this won't break older platforms. > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 8d86a39..1825ae7 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5231,12 +5231,10 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc) > int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) > { > /* > - * Account for spread spectrum to avoid > - * oversubscribing the link. Max center spread > - * is 2.5%; use 5% for safety's sake. > + * The spec says: > + * Number of lanes >= INT(dot clock * bytes per pixel / ls_clk) > */ > - u32 bps = target_clock * bpp * 21 / 20; > - return bps / (link_bw * 8) + 1; > + return DIV_ROUND_UP(target_clock * bpp, link_bw * 8); Can you split this into two patches, one for using DIV_ROUND_UP and for removingthe oversubscription, as the DIV_ROUND_UP looks to be a separate issue worth testing. (Handling the case where bps % (link_bw * 8) == 0.) -Chris -- Chris Wilson, Intel Open Source Technology Centre