From: Frederic Barrat <fbarrat@linux.ibm.com>
To: "Joel Stanley" <joel@jms.id.au>,
"Cédric Le Goater" <clg@kaod.org>,
"Nicholas Piggin" <npiggin@gmail.com>
Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Subject: Re: [PATCH v2 2/5] ppc/pnv: Subclass quad xscom callbacks
Date: Tue, 4 Jul 2023 11:59:57 +0200 [thread overview]
Message-ID: <6c4df06c-50be-797a-349b-51caf25156f4@linux.ibm.com> (raw)
In-Reply-To: <20230704054204.168547-3-joel@jms.id.au>
On 04/07/2023 07:42, Joel Stanley wrote:
> Make the existing pnv_quad_xscom_read/write be P9 specific, in
> preparation for a different P10 callback.
>
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Fred
> v2: Add scom region size to class
> ---
> include/hw/ppc/pnv_core.h | 13 ++++++++++++-
> hw/ppc/pnv.c | 11 +++++++----
> hw/ppc/pnv_core.c | 40 ++++++++++++++++++++++++++-------------
> 3 files changed, 46 insertions(+), 18 deletions(-)
>
> diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h
> index 3d75706e95da..77ef00f47a72 100644
> --- a/include/hw/ppc/pnv_core.h
> +++ b/include/hw/ppc/pnv_core.h
> @@ -60,8 +60,19 @@ static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
> return (PnvCPUState *)cpu->machine_data;
> }
>
> +struct PnvQuadClass {
> + DeviceClass parent_class;
> +
> + const MemoryRegionOps *xscom_ops;
> + uint64_t xscom_size;
> +};
> +
> #define TYPE_PNV_QUAD "powernv-cpu-quad"
> -OBJECT_DECLARE_SIMPLE_TYPE(PnvQuad, PNV_QUAD)
> +
> +#define PNV_QUAD_TYPE_SUFFIX "-" TYPE_PNV_QUAD
> +#define PNV_QUAD_TYPE_NAME(cpu_model) cpu_model PNV_QUAD_TYPE_SUFFIX
> +
> +OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD)
>
> struct PnvQuad {
> DeviceState parent_obj;
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index fc083173f346..c77fdb6747a4 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -1429,14 +1429,15 @@ static void pnv_chip_power9_instance_init(Object *obj)
> }
>
> static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
> - PnvCore *pnv_core)
> + PnvCore *pnv_core,
> + const char *type)
> {
> char eq_name[32];
> int core_id = CPU_CORE(pnv_core)->core_id;
>
> snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
> object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
> - sizeof(*eq), TYPE_PNV_QUAD,
> + sizeof(*eq), type,
> &error_fatal, NULL);
>
> object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
> @@ -1454,7 +1455,8 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
> for (i = 0; i < chip9->nr_quads; i++) {
> PnvQuad *eq = &chip9->quads[i];
>
> - pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
> + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> + PNV_QUAD_TYPE_NAME("power9"));
>
> pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
> &eq->xscom_regs);
> @@ -1666,7 +1668,8 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
> for (i = 0; i < chip10->nr_quads; i++) {
> PnvQuad *eq = &chip10->quads[i];
>
> - pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
> + pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4],
> + PNV_QUAD_TYPE_NAME("power9"));
>
> pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
> &eq->xscom_regs);
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index 0f451b3b6e1f..73d25409c937 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -407,12 +407,14 @@ static const MemoryRegionOps pnv_quad_power9_xscom_ops = {
> static void pnv_quad_realize(DeviceState *dev, Error **errp)
> {
> PnvQuad *eq = PNV_QUAD(dev);
> + PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq);
> char name[32];
>
> snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id);
> pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev),
> - &pnv_quad_power9_xscom_ops,
> - eq, name, PNV9_XSCOM_EQ_SIZE);
> + pqc->xscom_ops,
> + eq, name,
> + pqc->xscom_size);
> }
>
> static Property pnv_quad_properties[] = {
> @@ -420,6 +422,14 @@ static Property pnv_quad_properties[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> +static void pnv_quad_power9_class_init(ObjectClass *oc, void *data)
> +{
> + PnvQuadClass *pqc = PNV_QUAD_CLASS(oc);
> +
> + pqc->xscom_ops = &pnv_quad_power9_xscom_ops;
> + pqc->xscom_size = PNV9_XSCOM_EQ_SIZE;
> +}
> +
> static void pnv_quad_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -429,16 +439,20 @@ static void pnv_quad_class_init(ObjectClass *oc, void *data)
> dc->user_creatable = false;
> }
>
> -static const TypeInfo pnv_quad_info = {
> - .name = TYPE_PNV_QUAD,
> - .parent = TYPE_DEVICE,
> - .instance_size = sizeof(PnvQuad),
> - .class_init = pnv_quad_class_init,
> +static const TypeInfo pnv_quad_infos[] = {
> + {
> + .name = TYPE_PNV_QUAD,
> + .parent = TYPE_DEVICE,
> + .instance_size = sizeof(PnvQuad),
> + .class_size = sizeof(PnvQuadClass),
> + .class_init = pnv_quad_class_init,
> + .abstract = true,
> + },
> + {
> + .parent = TYPE_PNV_QUAD,
> + .name = PNV_QUAD_TYPE_NAME("power9"),
> + .class_init = pnv_quad_power9_class_init,
> + },
> };
>
> -static void pnv_core_register_types(void)
> -{
> - type_register_static(&pnv_quad_info);
> -}
> -
> -type_init(pnv_core_register_types)
> +DEFINE_TYPES(pnv_quad_infos);
next prev parent reply other threads:[~2023-07-04 10:02 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 5:41 [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10 Joel Stanley
2023-07-04 5:42 ` [PATCH v2 1/5] ppc/pnv: quad xscom callbacks are P9 specific Joel Stanley
2023-07-04 9:59 ` Frederic Barrat
2023-07-04 5:42 ` [PATCH v2 2/5] ppc/pnv: Subclass quad xscom callbacks Joel Stanley
2023-07-04 9:59 ` Frederic Barrat [this message]
2023-07-04 5:42 ` [PATCH v2 3/5] ppc/pnv: Add P10 quad xscom model Joel Stanley
2023-07-04 6:55 ` Cédric Le Goater
2023-07-04 10:11 ` Frederic Barrat
2023-07-04 5:42 ` [PATCH v2 4/5] ppc/pnv: Add P10 core " Joel Stanley
2023-07-04 6:55 ` Cédric Le Goater
2023-07-04 10:12 ` Frederic Barrat
2023-07-04 5:42 ` [PATCH v2 5/5] ppc/pnv: Return zero for core thread state xscom Joel Stanley
2023-07-04 10:12 ` Frederic Barrat
2023-07-04 23:12 ` [PATCH v2 0/5] ppc/pnv: Extend "quad" model for p10 Daniel Henrique Barboza
2023-07-05 1:15 ` Nicholas Piggin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=6c4df06c-50be-797a-349b-51caf25156f4@linux.ibm.com \
--to=fbarrat@linux.ibm.com \
--cc=clg@kaod.org \
--cc=joel@jms.id.au \
--cc=npiggin@gmail.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.