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envelope-from=calebs@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Caleb Schlossin On 8/31/26 7:30 AM, Saif Abrar wrote: > From: Saif Abrar > > Config-read the link-status register in the PCI-E macro, > Depending on the link-active bit, set the link-active status > in the HOTPLUG_STATUS and LINK_MANAGEMENT registers > Also, clear the Presence-status active low bit in HOTPLUG_STATUS reg > after config-reading the slot-status in the PCI-E macro. > > Signed-off-by: Saif Abrar > Reviewed-by: Michael S. Tsirkin > Reviewed-by: Caleb Schlossin > Reviewed-by: Aditya Gupta > --- > hw/pci-host/pnv_phb4.c | 74 +++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 73 insertions(+), 1 deletion(-) > > diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c > index b13165f84d..87446aedc8 100644 > --- a/hw/pci-host/pnv_phb4.c > +++ b/hw/pci-host/pnv_phb4.c > @@ -508,6 +508,34 @@ uint32_t get_exp_offset(PCIDevice *pdev) > return rpc->exp_offset; > } > > +/* > + * Config-read the link-status register in the PCI-E macro, > + * convert to LE and check the link-active bit. > + */ > +static uint32_t is_link_active(PnvPHB4 *phb) > +{ > + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); > + PCIDevice *pdev = pci_find_device(pci->bus, 0, 0); > + uint32_t exp_offset = get_exp_offset(pdev); > + > + return (be16_to_cpu(pnv_phb4_rc_config_read(phb, > + exp_offset + PCI_EXP_LNKSTA, 4)) & > + PCI_EXP_LNKSTA_DLLLA); > +} > + > +/* > + * Apply sticky-mask 's' to the reset-value 'v' and write to the address 'a'. > + * RC-config space values and masks are LE. > + * Method pnv_phb4_rc_config_read() returns BE, hence convert to LE. > + * Compute new value in LE domain. > + * New value computation using sticky-mask is in LE. > + * Convert the computed value from LE to BE before writing back. > + */ > +#define RC_CONFIG_STICKY_RESET(a, v, s) \ > + (pci_set_word(conf + (a), be16_to_cpu( \ > + (be16_to_cpu(pci_get_word(conf + (a))) & (s)) | \ > + ((v) & ~(s))))) > + > void pnv_phb4_cfg_core_reset(PCIDevice *d) > { > uint8_t *conf = d->config; > @@ -680,6 +708,11 @@ void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, > val = 0; > break; > > + case PHB_PCIE_HOTPLUG_STATUS: > + /* For normal operations, Simspeed diagnostic bit is always zero */ > + val &= PHB_PCIE_HPSTAT_SIMDIAG; > + break; > + > /* Read only registers */ > case PHB_CPU_LOADSTORE_STATUS: > case PHB_ETU_ERR_SUMMARY: > @@ -827,6 +860,10 @@ void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, > uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) > { > PnvPHB4 *phb = PNV_PHB4(opaque); > + /* Get the PCI-E capability offset from the root-port */ > + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); > + PCIDevice *pdev = pci_find_device(pci->bus, 0, 0); > + uint32_t exp_base = get_exp_offset(pdev); > uint64_t val; > > if ((off & 0xfffc) == PHB_CONFIG_DATA) { > @@ -895,8 +932,38 @@ uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) > val |= PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; > return val; > > + /* > + * Read PCI-E registers and set status for: > + * - Card present (active low bit 10) > + * - Link active (bit 12) > + */ > case PHB_PCIE_HOTPLUG_STATUS: > - /* Clear write-only bit */ > + /* > + * Presence-status bit hpi_present_n is active-low, with reset value 1. > + * Start by setting this bit to 1, indicating the card is not present. > + * Then check the PCI-E register and clear the bit if card is present. > + */ > + val |= PHB_PCIE_HPSTAT_PRESENCE; > + > + /* > + * Config-read the PCI-E macro register for slot-status. > + * Method for config-read converts to BE value. > + * To check actual bit in the PCI-E register, > + * convert the value back to host format. > + * Clear the Presence-status active low bit. > + */ > + if (be16_to_cpu(pnv_phb4_rc_config_read(phb, exp_base + PCI_EXP_SLTSTA, > + 4)) > + & PCI_EXP_SLTSTA_PDS) { > + val &= ~PHB_PCIE_HPSTAT_PRESENCE; > + } > + > + /* Check if link is active and set the bit */ > + if (is_link_active(phb)) { > + val |= PHB_PCIE_HPSTAT_LINKACTIVE; > + } > + > + /* Clear write-only resample-bit */ > val &= ~PHB_PCIE_HPSTAT_RESAMPLE; > return val; > > @@ -904,6 +971,11 @@ uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) > case PHB_PCIE_LMR: > /* These write-only bits always read as 0 */ > val &= ~(PHB_PCIE_LMR_CHANGELW | PHB_PCIE_LMR_RETRAINLINK); > + > + /* Check if link is active and set the bit */ > + if (is_link_active(phb)) { > + val |= PHB_PCIE_LMR_LINKACTIVE; > + } > return val; > > /* Silent simple reads */