From: "Guo, Jia" <jia.guo@intel.com>
To: "Jiang, JunyuX" <junyux.jiang@intel.com>, "dev@dpdk.org" <dev@dpdk.org>
Cc: "Xing, Beilei" <beilei.xing@intel.com>,
"stable@dpdk.org" <stable@dpdk.org>
Subject: Re: [dpdk-dev] [PATCH v2] net/i40e: fix incorrect byte counters
Date: Wed, 16 Sep 2020 05:21:54 +0000 [thread overview]
Message-ID: <6d9cb7baf08e4564ba3db80a6a2f6764@intel.com> (raw)
In-Reply-To: <20200916015105.39815-1-junyux.jiang@intel.com>
Acked-by: Jeff Guo <jia.guo@intel.com>
> -----Original Message-----
> From: Jiang, JunyuX <junyux.jiang@intel.com>
> Sent: Wednesday, September 16, 2020 9:51 AM
> To: dev@dpdk.org
> Cc: Guo, Jia <jia.guo@intel.com>; Xing, Beilei <beilei.xing@intel.com>; Jiang,
> JunyuX <junyux.jiang@intel.com>; stable@dpdk.org
> Subject: [PATCH v2] net/i40e: fix incorrect byte counters
>
> This patch fixed the issue that rx/tx bytes overflowed on 48 bit limitation by
> enlarging the limitation.
>
> Fixes: 4861cde46116 ("i40e: new poll mode driver")
> Cc: stable@dpdk.org
>
> Signed-off-by: Junyu Jiang <junyux.jiang@intel.com>
> ---
> drivers/net/i40e/i40e_ethdev.c | 47
> ++++++++++++++++++++++++++++++++++
> drivers/net/i40e/i40e_ethdev.h | 9 +++++++
> 2 files changed, 56 insertions(+)
>
> diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
> index 563f21d9d..4d4ea9861 100644
> --- a/drivers/net/i40e/i40e_ethdev.c
> +++ b/drivers/net/i40e/i40e_ethdev.c
> @@ -3073,6 +3073,13 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi)
> i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx),
> I40E_GLV_BPRCL(idx),
> vsi->offset_loaded, &oes->rx_broadcast,
> &nes->rx_broadcast);
> + /* enlarge the limitation when rx_bytes overflowed */
> + if (vsi->offset_loaded) {
> + if (I40E_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes-
> >rx_bytes)
> + nes->rx_bytes += (uint64_t)1 << I40E_48_BIT_WIDTH;
> + nes->rx_bytes += I40E_RXTX_BYTES_HIGH(vsi-
> >old_rx_bytes);
> + }
> + vsi->old_rx_bytes = nes->rx_bytes;
> /* exclude CRC bytes */
> nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
> nes->rx_broadcast) * RTE_ETHER_CRC_LEN; @@ -3099,6
> +3106,13 @@ i40e_update_vsi_stats(struct i40e_vsi *vsi)
> /* GLV_TDPC not supported */
> i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
> &oes->tx_errors, &nes->tx_errors);
> + /* enlarge the limitation when tx_bytes overflowed */
> + if (vsi->offset_loaded) {
> + if (I40E_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes-
> >tx_bytes)
> + nes->tx_bytes += (uint64_t)1 << I40E_48_BIT_WIDTH;
> + nes->tx_bytes += I40E_RXTX_BYTES_HIGH(vsi-
> >old_tx_bytes);
> + }
> + vsi->old_tx_bytes = nes->tx_bytes;
> vsi->offset_loaded = true;
>
> PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start
> *******************", @@ -3171,6 +3185,24 @@
> i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
> pf->offset_loaded,
> &pf->internal_stats_offset.tx_broadcast,
> &pf->internal_stats.tx_broadcast);
> + /* enlarge the limitation when internal rx/tx bytes overflowed */
> + if (pf->offset_loaded) {
> + if (I40E_RXTX_BYTES_LOW(pf->internal_old_rx_bytes) >
> + pf->internal_stats.rx_bytes)
> + pf->internal_stats.rx_bytes +=
> + (uint64_t)1 << I40E_48_BIT_WIDTH;
> + pf->internal_stats.rx_bytes +=
> + I40E_RXTX_BYTES_HIGH(pf->internal_old_rx_bytes);
> +
> + if (I40E_RXTX_BYTES_LOW(pf->internal_old_tx_bytes) >
> + pf->internal_stats.tx_bytes)
> + pf->internal_stats.tx_bytes +=
> + (uint64_t)1 << I40E_48_BIT_WIDTH;
> + pf->internal_stats.tx_bytes +=
> + I40E_RXTX_BYTES_HIGH(pf->internal_old_tx_bytes);
> + }
> + pf->internal_old_rx_bytes = pf->internal_stats.rx_bytes;
> + pf->internal_old_tx_bytes = pf->internal_stats.tx_bytes;
>
> /* exclude CRC size */
> pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast + @@ -
> 3194,6 +3226,14 @@ i40e_read_stats_registers(struct i40e_pf *pf, struct
> i40e_hw *hw)
> I40E_GLPRT_BPRCL(hw->port),
> pf->offset_loaded, &os->eth.rx_broadcast,
> &ns->eth.rx_broadcast);
> + /* enlarge the limitation when rx_bytes overflowed */
> + if (pf->offset_loaded) {
> + if (I40E_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns-
> >eth.rx_bytes)
> + ns->eth.rx_bytes += (uint64_t)1 <<
> I40E_48_BIT_WIDTH;
> + ns->eth.rx_bytes += I40E_RXTX_BYTES_HIGH(pf-
> >old_rx_bytes);
> + }
> + pf->old_rx_bytes = ns->eth.rx_bytes;
> +
> /* Workaround: CRC size should not be included in byte statistics,
> * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
> * packet.
> @@ -3252,6 +3292,13 @@ i40e_read_stats_registers(struct i40e_pf *pf,
> struct i40e_hw *hw)
> I40E_GLPRT_BPTCL(hw->port),
> pf->offset_loaded, &os->eth.tx_broadcast,
> &ns->eth.tx_broadcast);
> + /* enlarge the limitation when tx_bytes overflowed */
> + if (pf->offset_loaded) {
> + if (I40E_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns-
> >eth.tx_bytes)
> + ns->eth.tx_bytes += (uint64_t)1 <<
> I40E_48_BIT_WIDTH;
> + ns->eth.tx_bytes += I40E_RXTX_BYTES_HIGH(pf-
> >old_tx_bytes);
> + }
> + pf->old_tx_bytes = ns->eth.tx_bytes;
> ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
> ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
>
> diff --git a/drivers/net/i40e/i40e_ethdev.h
> b/drivers/net/i40e/i40e_ethdev.h index 19f821829..5d17be1f0 100644
> --- a/drivers/net/i40e/i40e_ethdev.h
> +++ b/drivers/net/i40e/i40e_ethdev.h
> @@ -282,6 +282,9 @@ struct rte_flow {
> #define I40E_ETH_OVERHEAD \
> (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN +
> I40E_VLAN_TAG_SIZE * 2)
>
> +#define I40E_RXTX_BYTES_HIGH(bytes) ((bytes) & ~I40E_48_BIT_MASK)
> +#define I40E_RXTX_BYTES_LOW(bytes) ((bytes) & I40E_48_BIT_MASK)
> +
> struct i40e_adapter;
> struct rte_pci_driver;
>
> @@ -399,6 +402,8 @@ struct i40e_vsi {
> uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
> uint8_t vlan_filter_on; /* The VLAN filter enabled */
> struct i40e_bw_info bw_info; /* VSI bandwidth information */
> + uint64_t old_rx_bytes;
> + uint64_t old_tx_bytes;
> };
>
> struct pool_entry {
> @@ -1156,6 +1161,10 @@ struct i40e_pf {
> uint16_t switch_domain_id;
>
> struct i40e_vf_msg_cfg vf_msg_cfg;
> + uint64_t old_rx_bytes;
> + uint64_t old_tx_bytes;
> + uint64_t internal_old_rx_bytes;
> + uint64_t internal_old_tx_bytes;
> };
>
> enum pending_msg {
> --
> 2.17.1
next prev parent reply other threads:[~2020-09-16 5:22 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-10 1:54 [dpdk-dev] [PATCH] net/i40e: fix incorrect byte counters Junyu Jiang
2020-09-10 2:18 ` [dpdk-dev] [dpdk-stable] " Han, YingyaX
2020-09-10 5:58 ` Guo, Jia
2020-09-10 6:45 ` Jiang, JunyuX
2020-09-16 1:51 ` [dpdk-dev] [PATCH v2] " Junyu Jiang
2020-09-16 2:39 ` [dpdk-dev] [dpdk-stable] " Han, YingyaX
2020-09-16 5:21 ` Guo, Jia [this message]
2020-09-16 5:50 ` [dpdk-dev] " Zhang, Qi Z
2020-09-16 12:30 ` [dpdk-dev] [dpdk-stable] " Ferruh Yigit
2020-09-18 3:44 ` Jiang, JunyuX
2020-09-18 9:23 ` Igor Ryzhov
2020-09-18 13:42 ` Ferruh Yigit
2020-09-21 1:55 ` Jiang, JunyuX
2020-09-18 13:37 ` Ferruh Yigit
2020-09-21 9:59 ` [dpdk-dev] [PATCH v3] " Junyu Jiang
2020-09-21 11:41 ` Ferruh Yigit
2020-09-22 7:37 ` [dpdk-dev] [PATCH v4] " Junyu Jiang
2020-09-22 9:06 ` Ferruh Yigit
2020-09-22 9:19 ` [dpdk-dev] [PATCH v5] " Junyu Jiang
2020-09-22 12:59 ` Zhang, Qi Z
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=6d9cb7baf08e4564ba3db80a6a2f6764@intel.com \
--to=jia.guo@intel.com \
--cc=beilei.xing@intel.com \
--cc=dev@dpdk.org \
--cc=junyux.jiang@intel.com \
--cc=stable@dpdk.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.