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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a6fcf56073bsm185617566b.169.2024.06.22.04.46.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 22 Jun 2024 04:46:13 -0700 (PDT) Message-ID: <6e7e7b44-3c06-42ce-9d9b-9dcc83387657@linaro.org> Date: Sat, 22 Jun 2024 13:46:10 +0200 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/7] ARM: dts: qcom: msm8226: Add CPU frequency scaling support To: Luca Weiss , ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Michael Turquette , Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org References: <20240619-msm8226-cpufreq-v1-0-85143f5291d1@lucaweiss.eu> <20240619-msm8226-cpufreq-v1-5-85143f5291d1@lucaweiss.eu> Content-Language: en-US From: Konrad Dybcio Autocrypt: addr=konrad.dybcio@linaro.org; keydata= xsFNBF9ALYUBEADWAhxdTBWrwAgDQQzc1O/bJ5O7b6cXYxwbBd9xKP7MICh5YA0DcCjJSOum BB/OmIWU6X+LZW6P88ZmHe+KeyABLMP5s1tJNK1j4ntT7mECcWZDzafPWF4F6m4WJOG27kTJ HGWdmtO+RvadOVi6CoUDqALsmfS3MUG5Pj2Ne9+0jRg4hEnB92AyF9rW2G3qisFcwPgvatt7 TXD5E38mLyOPOUyXNj9XpDbt1hNwKQfiidmPh5e7VNAWRnW1iCMMoKqzM1Anzq7e5Afyeifz zRcQPLaqrPjnKqZGL2BKQSZDh6NkI5ZLRhhHQf61fkWcUpTp1oDC6jWVfT7hwRVIQLrrNj9G MpPzrlN4YuAqKeIer1FMt8cq64ifgTzxHzXsMcUdclzq2LTk2RXaPl6Jg/IXWqUClJHbamSk t1bfif3SnmhA6TiNvEpDKPiT3IDs42THU6ygslrBxyROQPWLI9IL1y8S6RtEh8H+NZQWZNzm UQ3imZirlPjxZtvz1BtnnBWS06e7x/UEAguj7VHCuymVgpl2Za17d1jj81YN5Rp5L9GXxkV1 aUEwONM3eCI3qcYm5JNc5X+JthZOWsbIPSC1Rhxz3JmWIwP1udr5E3oNRe9u2LIEq+wH/toH kpPDhTeMkvt4KfE5m5ercid9+ZXAqoaYLUL4HCEw+HW0DXcKDwARAQABzShLb25yYWQgRHli Y2lvIDxrb25yYWQuZHliY2lvQGxpbmFyby5vcmc+wsGOBBMBCAA4FiEEU24if9oCL2zdAAQV R4cBcg5dfFgFAmQ5bqwCGwMFCwkIBwIGFQoJCAsCBBYCAwECHgECF4AACgkQR4cBcg5dfFjO BQ//YQV6fkbqQCceYebGg6TiisWCy8LG77zV7DB0VMIWJv7Km7Sz0QQrHQVzhEr3trNenZrf yy+o2tQOF2biICzbLM8oyQPY8B///KJTWI2khoB8IJSJq3kNG68NjPg2vkP6CMltC/X3ohAo xL2UgwN5vj74QnlNneOjc0vGbtA7zURNhTz5P/YuTudCqcAbxJkbqZM4WymjQhe0XgwHLkiH 5LHSZ31MRKp/+4Kqs4DTXMctc7vFhtUdmatAExDKw8oEz5NbskKbW+qHjW1XUcUIrxRr667V GWH6MkVceT9ZBrtLoSzMLYaQXvi3sSAup0qiJiBYszc/VOu3RbIpNLRcXN3KYuxdQAptacTE mA+5+4Y4DfC3rUSun+hWLDeac9z9jjHm5rE998OqZnOU9aztbd6zQG5VL6EKgsVXAZD4D3RP x1NaAjdA3MD06eyvbOWiA5NSzIcC8UIQvgx09xm7dThCuQYJR4Yxjd+9JPJHI6apzNZpDGvQ BBZzvwxV6L1CojUEpnilmMG1ZOTstktWpNzw3G2Gis0XihDUef0MWVsQYJAl0wfiv/0By+XK mm2zRR+l/dnzxnlbgJ5pO0imC2w0TVxLkAp0eo0LHw619finad2u6UPQAkZ4oj++iIGrJkt5 Lkn2XgB+IW8ESflz6nDY3b5KQRF8Z6XLP0+IEdLOOARkOW7yEgorBgEEAZdVAQUBAQdAwmUx xrbSCx2ksDxz7rFFGX1KmTkdRtcgC6F3NfuNYkYDAQgHwsF2BBgBCAAgFiEEU24if9oCL2zd AAQVR4cBcg5dfFgFAmQ5bvICGwwACgkQR4cBcg5dfFju1Q//Xta1ShwL0MLSC1KL1lXGXeRM 8arzfyiB5wJ9tb9U/nZvhhdfilEDLe0jKJY0RJErbdRHsalwQCrtq/1ewQpMpsRxXzAjgfRN jc4tgxRWmI+aVTzSRpywNahzZBT695hMz81cVZJoZzaV0KaMTlSnBkrviPz1nIGHYCHJxF9r cIu0GSIyUjZ/7xslxdvjpLth16H27JCWDzDqIQMtg61063gNyEyWgt1qRSaK14JIH/DoYRfn jfFQSC8bffFjat7BQGFz4ZpRavkMUFuDirn5Tf28oc5ebe2cIHp4/kajTx/7JOxWZ80U70mA cBgEeYSrYYnX+UJsSxpzLc/0sT1eRJDEhI4XIQM4ClIzpsCIN5HnVF76UQXh3a9zpwh3dk8i bhN/URmCOTH+LHNJYN/MxY8wuukq877DWB7k86pBs5IDLAXmW8v3gIDWyIcgYqb2v8QO2Mqx YMqL7UZxVLul4/JbllsQB8F/fNI8AfttmAQL9cwo6C8yDTXKdho920W4WUR9k8NT/OBqWSyk bGqMHex48FVZhexNPYOd58EY9/7mL5u0sJmo+jTeb4JBgIbFPJCFyng4HwbniWgQJZ1WqaUC nas9J77uICis2WH7N8Bs9jy0wQYezNzqS+FxoNXmDQg2jetX8en4bO2Di7Pmx0jXA4TOb9TM izWDgYvmBE8= In-Reply-To: <20240619-msm8226-cpufreq-v1-5-85143f5291d1@lucaweiss.eu> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 19.06.2024 11:02 PM, Luca Weiss wrote: > Add a node for the a7pll with its frequencies. With this we can use the > apcs-kpss-global driver for the apcs node and use the apcs to scale the > CPU frequency according to the opp-table. > > At the same time unfortunately we need to provide the gcc node xo_board > instead of the XO via rpmcc since otherwise we'll have a circular > dependency between apcs, gcc and the rpm. Hm.. thinking of a solution to that, should we maybe split the mux/clk part of APCS into a subnode and bind the clk device to that? Dmitry, Bjorn, thoughts? [...] > + > + opp-600000000 { Can't find this one in the random msm-3.10 I have > + opp-hz = /bits/ 64 <600000000>; > + }; > + > + opp-787200000 { > + opp-hz = /bits/ 64 <787200000>; > + }; > + > + /* Higher CPU frequencies need speedbin support */ 1190400 kHz seems to also be a supported-across-the-board one.. unless the watch edition shuffled things around with a newer tree > + }; > + > pmu { > compatible = "arm,cortex-a7-pmu"; > interrupts = @@ -231,9 +262,75 @@ intc: interrupt-controller@f9000000 { > #interrupt-cells = <3>; > }; > > - apcs: syscon@f9011000 { > - compatible = "syscon"; > + apcs: mailbox@f9011000 { > + compatible = "qcom,msm8226-apcs-kpss-global", > + "qcom,msm8916-apcs-kpss-global", "syscon"; > reg = <0xf9011000 0x1000>; > + #mbox-cells = <1>; > + clocks = <&a7pll>, <&gcc GPLL0_VOTE>; > + clock-names = "pll", "aux"; > + #clock-cells = <0>; > + }; > + > + a7pll: clock@f9016000 { > + compatible = "qcom,msm8226-a7pll"; > + reg = <0xf9016000 0x40>; > + #clock-cells = <0>; > + clocks = <&xo_board>; > + clock-names = "xo"; > + operating-points-v2 = <&a7pll_opp_table>; > + > + a7pll_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-768000000 { > + opp-hz = /bits/ 64 <768000000>; > + }; Looks like scaling this PLL should also scale some voltage domains: CPR (fed by pm8226_s2) and MX Perhaps hook up MX to this one for now and add CPR to the CPU nodes( & OPP table) after that is brought up Konrad