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From: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
	Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>,
	Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com>,
	Andi Shyti <andi.shyti@kernel.org>,
	Manikanta Mylavarapu <quic_mmanikan@quicinc.com>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>
Cc: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>,
	linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] i2c: qcom-geni: add I2C frequency table for 32 MHz firmware-based SEs
Date: Wed, 26 Aug 2026 22:27:00 +0530	[thread overview]
Message-ID: <6ec861d5-c31e-4b32-a59f-17da3017edee@oss.qualcomm.com> (raw)
In-Reply-To: <30a04183-b8d5-4a6d-8092-6b888a240410@oss.qualcomm.com>


On 8/24/2026 2:54 PM, Konrad Dybcio wrote:
> On 8/12/26 10:30 AM, Kathiravan Thirumoorthy wrote:
>> On IPQ5424, the I2C controller can operate on both RTL-hardened SEs
>> and firmware-based SEs. As documented in commit 506bb2ab0075
>> ("i2c: qcom-geni: Support systems with 32MHz serial engine clock"),
>> in IPQ5424 SEs use a 32 MHz source clock.
>>
>> The existing frequency table does not provide the required SCL timing
>> parameters for firmware-based SEs. Add a dedicated frequency table
>> using the SCL counter values recommended by the hardware design team
>> and select it for firmware-based SEs to achieve the target bus
>> frequencies.
>>
>> Move geni_i2c_clk_map_idx() from geni_i2c_resources_init() to
>> geni_i2c_init() to ensure SE_HW_PARAM_2 is accessed only after the
>> required clocks have been enabled.
>>
>> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
>> ---
>>   drivers/i2c/busses/i2c-qcom-geni.c | 25 ++++++++++++++++++-------
>>   include/linux/soc/qcom/geni-se.h   |  1 +
>>   2 files changed, 19 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
>> index 00013b41a6f5..15835f10b062 100644
>> --- a/drivers/i2c/busses/i2c-qcom-geni.c
>> +++ b/drivers/i2c/busses/i2c-qcom-geni.c
>> @@ -187,19 +187,28 @@ static const struct geni_i2c_clk_fld geni_i2c_clk_map_19p2mhz[] = {
>>   };
>>   
>>   /* source_clock = 32 MHz */
>> -static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = {
>> +static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz_minicore[] = {
>>   	{ I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 26 },
>>   	{ I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 },
>>   	{ I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 },
>>   	{}
>>   };
>>   
>> +static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz_fwcore[] = {
>> +	{ I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 25 },
>> +	{ I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 18 },
>> +	{ I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 6, 15, 29 },
>> +	{}
>> +};
> The fwcore one seems to be slightly "stricter" - wouldn't it work
> for both of them?

No, We are not able to achieve the desired frequency. So based on design 
team's feedback, we are using separate configurations.

>
> Konrad

  reply	other threads:[~2026-08-26 16:57 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-12  8:30 [PATCH v2 0/2] I2C SCL counter updates for Qualcomm IPQ5424 SoC Kathiravan Thirumoorthy
2026-08-12  8:30 ` [PATCH v2 1/2] i2c: qcom-geni: update frequency table to fix timing parameters Kathiravan Thirumoorthy
2026-08-12 17:45   ` Mukesh Savaliya
2026-08-17 13:55   ` Konrad Dybcio
2026-08-18 10:58     ` Kathiravan Thirumoorthy
2026-08-24  9:22       ` Konrad Dybcio
2026-08-28  0:31   ` Andi Shyti
2026-08-12  8:30 ` [PATCH v2 2/2] i2c: qcom-geni: add I2C frequency table for 32 MHz firmware-based SEs Kathiravan Thirumoorthy
2026-08-12 17:56   ` Mukesh Savaliya
2026-08-24  9:24   ` Konrad Dybcio
2026-08-26 16:57     ` Kathiravan Thirumoorthy [this message]
2026-08-25 17:20   ` Praveen Talari
2026-08-26 16:59     ` Kathiravan Thirumoorthy
2026-08-26 17:25       ` Praveen Talari

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