From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 15 Jan 2019 14:12:29 -0000 Received: from smtp.ctxuk.citrix.com ([185.25.65.24] helo=SMTP.EU.CITRIX.COM) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1gjPS8-0002am-8H for speck@linutronix.de; Tue, 15 Jan 2019 15:12:28 +0100 Subject: [MODERATED] Re: [PATCH v4 01/28] MDSv4 3 References: <2a7a23c9c36cff225e2fcb80c09c3d369d9a7331.1547256470.git.ak@linux.intel.com> From: Andrew Cooper Message-ID: <6f34be1f-47d3-5188-c093-b06e47fa384d@citrix.com> Date: Tue, 15 Jan 2019 14:11:30 +0000 MIME-Version: 1.0 In-Reply-To: <2a7a23c9c36cff225e2fcb80c09c3d369d9a7331.1547256470.git.ak@linux.intel.com> Content-Type: multipart/mixed; boundary="cuDn2JPqHJUL4eRPutYjDnaL12CWNgzlx"; protected-headers="v1" To: speck@linutronix.de List-ID: --cuDn2JPqHJUL4eRPutYjDnaL12CWNgzlx Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Content-Language: en-GB On 12/01/2019 01:29, speck for Andi Kleen wrote: > @@ -1019,6 +1027,12 @@ static void __init cpu_set_bug_bits(struct cpuin= fo_x86 *c) > if (ia32_cap & ARCH_CAP_IBRS_ALL) > setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED); > =20 > + if ((boot_cpu_data.x86_vendor =3D=3D X86_VENDOR_INTEL && > + !x86_match_cpu(cpu_no_mds)) && > + !(ia32_cap & ARCH_CAP_MDS_NO) && > + !(ia32_cap & ARCH_CAP_RDCL_NO)) > + setup_force_cpu_bug(X86_BUG_MDS); According to the latest doc I've got, RDCL_NO only indicates the absence of MFBDS (FBBF), while MSBDS (PSF) and MLPDS (SVL)=C2=A0 are still presen= t. It is only MDS_NO which indicates the absence of all the issues. Furthermore, looking at the giant affected matrix, I see no processors which are affected by FBBF but not by PSF, so unless we've decided that we don't care about PSF and SVL, workarounds still need to be used even when RDCL_NO is asserted. ~Andrew --cuDn2JPqHJUL4eRPutYjDnaL12CWNgzlx--