From mboxrd@z Thu Jan  1 00:00:00 1970
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From: "Siegmund, Jan" <jan.siegmund0@hm.edu>
Subject: WG: Linux hang
Date: Thu, 7 Dec 2017 11:00:45 +0000
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To: "u-boot@lists.denx.de" <u-boot@lists.denx.de>
Cc: "linux-fpga@vger.kernel.org" <linux-fpga@vger.kernel.org>

Hi all,
does anybody have an idea for the following problem?

* FPGA is programmed using an overlay
* FPGA writes to SDRAM via the FPGA2SDRAM-bridge
* Linux hangs and the watchdog resets the board (the FPGA stays programmed)
* After the reset and boot, the FPGA is reprogrammed using the same overlay
* Now, the FPGA can write to the SDRAM without a problem

The environment:

*Board:�� DE0-NANO-SoC
*U-Boot: 2017.11
*Kernel:� 4.14.0-rc7 (review-v4.14-rc7-non-dt-support-v5.1 branch)

The overlay:

/dts-v1/;
/plugin/;

/ {
������� fragment@0 {
��������������� target-path = "/soc/base_fpga_region";
��������������� #address-cells = <1>;
��������������� #size-cells = <1>;
��������������� __overlay__ {
����������������������� #address-cells = <1>;
����������������������� #size-cells = <1>;
����������������������� fpga-bridges = <&fpga_bridge0 &fpga_bridge1>;
����������������������� firmware-name = "foo_base.rbf";

����������������������� fpga-bridge@ffc25080 {
������������������������������� compatible = "altr,socfpga-fpga2sdram-bridge";
������������������������������� reg = <0xffc25080 0x4>;
������������������������������� bridge-enable = <1>;
����������������������� };

����������������������� foo@ff200000 {
������������������������������� compatible= "altr,bar";
������������������������������� interrupt-parent = <&intc>;
������������������������������� interrupts = <0 40 4>;
����������������������� };

��������������� };
������� };
};

Thanks
From mboxrd@z Thu Jan  1 00:00:00 1970
From: Siegmund, Jan <jan.siegmund0@hm.edu>
Date: Thu, 7 Dec 2017 11:00:45 +0000
Subject: [U-Boot] WG: Linux hang
In-Reply-To: <4d6911ffa53349b0881ff4d4845bc101@hm.edu>
References: <4d6911ffa53349b0881ff4d4845bc101@hm.edu>
Message-ID: <71bcb4759caa437dba81be27fc611239@hm.edu>
List-Id: <u-boot.lists.denx.de>
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Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 8bit
To: u-boot@lists.denx.de

Hi all,
does anybody have an idea for the following problem?

* FPGA is programmed using an overlay
* FPGA writes to SDRAM via the FPGA2SDRAM-bridge
* Linux hangs and the watchdog resets the board (the FPGA stays programmed)
* After the reset and boot, the FPGA is reprogrammed using the same overlay
* Now, the FPGA can write to the SDRAM without a problem

The environment:

*Board:   DE0-NANO-SoC
*U-Boot: 2017.11
*Kernel:  4.14.0-rc7 (review-v4.14-rc7-non-dt-support-v5.1 branch)

The overlay:

/dts-v1/;
/plugin/;

/ {
        fragment at 0 {
                target-path = "/soc/base_fpga_region";
                #address-cells = <1>;
                #size-cells = <1>;
                __overlay__ {
                        #address-cells = <1>;
                        #size-cells = <1>;
                        fpga-bridges = <&fpga_bridge0 &fpga_bridge1>;
                        firmware-name = "foo_base.rbf";

                        fpga-bridge at ffc25080 {
                                compatible = "altr,socfpga-fpga2sdram-bridge";
                                reg = <0xffc25080 0x4>;
                                bridge-enable = <1>;
                        };

                        foo at ff200000 {
                                compatible= "altr,bar";
                                interrupt-parent = <&intc>;
                                interrupts = <0 40 4>;
                        };

                };
        };
};

Thanks