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Tue, 14 Jan 2025 05:08:11 -0800 (PST) Received: from [192.168.68.110] ([189.110.107.205]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5f88266e273sm4209793eaf.26.2025.01.14.05.08.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Jan 2025 05:08:10 -0800 (PST) Message-ID: <72c3e437-1a2c-49e8-90ed-61ce1b1f5342@ventanamicro.com> Date: Tue, 14 Jan 2025 10:08:06 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] hw/intc/riscv_aplic: Remove redundant masking of hart_idx in riscv_aplic_msi_send() To: Huang Borong , palmer@dabbelt.com, alistair.francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org References: <20250114025320.52696-1-huangborong@bosc.ac.cn> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20250114025320.52696-1-huangborong@bosc.ac.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On 1/13/25 11:53 PM, Huang Borong wrote: > The line "hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw);" was removed > because the same operation is performed later in the address calculation. > This change improves code clarity and avoids unnecessary operations. > > Signed-off-by: Huang Borong > --- > hw/intc/riscv_aplic.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c > index 4866649115..0974c6a5db 100644 > --- a/hw/intc/riscv_aplic.c > +++ b/hw/intc/riscv_aplic.c > @@ -421,7 +421,6 @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic, > APLIC_xMSICFGADDRH_HHXW_MASK; > > group_idx = hart_idx >> lhxw; > - hart_idx &= APLIC_xMSICFGADDR_PPN_LHX_MASK(lhxw); It is worth noticing that this will change 'hart_idx' in the qemu_log_mask() in the end: if (result != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "%s: MSI write failed for " "hart_index=%d guest_index=%d eiid=%d\n", __func__, hart_idx, guest_idx, eiid); } But I believe 'hart_idx' in that context should be the original 'hart_idx' parameter, not the masked value like we're doing today. Reviewed-by: Daniel Henrique Barboza > > addr = msicfgaddr; > addr |= ((uint64_t)(msicfgaddrH & APLIC_xMSICFGADDRH_BAPPN_MASK)) << 32;