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Thu, 06 Aug 2026 16:50:14 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (smtpav04.fra02v.mail.ibm.com [10.20.54.103]) by smtprelay06.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 676Go8OS30933476 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 6 Aug 2026 16:50:08 GMT Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C1C3120043; Thu, 6 Aug 2026 16:50:08 +0000 (GMT) Received: from smtpav04.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 11FB120040; Thu, 6 Aug 2026 16:50:04 +0000 (GMT) Received: from [9.67.65.218] (unknown [9.67.65.218]) by smtpav04.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 6 Aug 2026 16:50:03 +0000 (GMT) Message-ID: <72ce5fa7-d12b-40e5-a4a2-f2de414088d1@linux.ibm.com> Date: Thu, 6 Aug 2026 22:20:02 +0530 X-Mailing-List: linuxppc-dev@lists.ozlabs.org List-Id: List-Help: List-Owner: List-Post: List-Archive: , List-Subscribe: , , List-Unsubscribe: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] PCI: quirks: Add warm reset quirk for IBM Spyre accelerator To: Bjorn Helgaas , Avinash Roy Cc: maddy@linux.ibm.com, mpe@ellerman.id.au, bhelgaas@google.com, npiggin@gmail.com, chleroy@kernel.org, linuxppc-dev@lists.ozlabs.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Avinash Roy References: <20260805171840.GA2126423@bhelgaas> Content-Language: en-US From: Shivaprasad G Bhat In-Reply-To: <20260805171840.GA2126423@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Authority-Analysis: v=2.4 cv=E6P9Y6dl c=1 sm=1 tr=0 ts=6a74bb47 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=lNBmhb5rY3KJr28suEEA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: A9CrAhuigwKofBxmnfCcLJ4S9jqP9RFJ X-Proofpoint-GUID: LvFnR9t07Rol95n-wE_uOh-qTWiH2Xy5 X-Proofpoint-Spam-Info: AW1haW4tMjYwODA2MDEzMSBTYWx0ZWRfX0srVlo17IyM8 GCHvlg1eoQf97TwPNmj+IylyERYu1FuQTYWGmHs50pmU+6n2tg6c0oSLjGXSbrhEoHYhQWc8VOv UdNoe+xstgmTo7URo3sFwRlW3YQecTw= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA2MDEzMSBTYWx0ZWRfX30k6tIyX9/0Y hVu7CVXerDNsdRZJrSmUneKKfa3juUzkXerZqx+WirCXg/F2vfcpx/mY1HSK3ova3muZyDR+S+F Hq53TLO/FazxXFQ1hKKGINeRxJjurSA0g4u6B4gKjT1k1+nlTOfqFz86ySi0yrrXU6YMieGduQo x25UeGLgZEHHkyAN2JELunV5ridXnuO7zLv2jC+w4PAC4xiQ1mZ8RWf500JGH0wpo9oepIb+itM q4jeQxrN5bKhwDMo1uibRRPtQv7MxJ79gUWPpT159LewXCX9mOBanP/NSt9wRq2ORzrZklPlBs/ /j6m+PYBpXFS7sXl9Hdci90tFoZbshL0efZPKuygf+odI70Aj/9HPk0ymazRuXVcKTCPJpF9JLG ChLELbKXInS8PqDr2ydbS3F0C+i6oxT6A7/2NsoDXQw/4ANKvXqh2OZzUDwcnsPlWCo6Yjh+iAj CXRbGxkcql8Y62t3I6w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-06_01,2026-08-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1011 lowpriorityscore=0 priorityscore=1501 suspectscore=0 adultscore=0 spamscore=0 malwarescore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608060131 Hi Bjorn, Thanks for taking a look. On 8/5/26 10:48 PM, Bjorn Helgaas wrote: > On Wed, Aug 05, 2026 at 06:21:32PM +0530, Avinash Roy wrote: >> From: Shivaprasad G Bhat >> >> The IBM Spyre accelerator (PCI ID 1014:06a7) requires a dedicated warm >> reset method for reliable EEH recovery on pSeries/ppc64 platforms. >> >> FLR alone is insufficient because it does not re-initialize the Spyre >> firmware state machine. On ppc64 with EEH enabled, >> pcibios_set_pcie_reset_state() is overridden in >> arch/powerpc/kernel/eeh.c to drive the platform-level PERST# signal via >> EEH PE operations, which is the correct mechanism for full device >> recovery after an EEH event. > > This makes it sound like this mechanism is needed for EEH recovery for > *all* devices, not just Spyre. If that's the case it sounds like we > need more than just a Spyre-specific quirk. Now I re-read it, The second statement needs to be re-worded. It does sound like its true for all devices. Quirk is only for the Spyre card. Will post a v2 fixing the same. Thanks and Regards, Shivaprasad > >> The reset function is placed in arch/powerpc/platforms/pseries/pci.c >> where the EEH infrastructure is already present, declared in >> pseries.h, and registered in the generic pci_dev_reset_methods[] table >> in drivers/pci/quirks.c under a CONFIG_PPC_PSERIES guard. >> >> This reset method is only registered when CONFIG_PPC_PSERIES is enabled, >> so it is not available on other platforms. >> >> Reset sequence: >> - Assert PERST# via pcie_warm_reset, hold 250 ms >> - Deassert PERST# via pcie_deassert_reset >> - Wait 250 ms for PCIe link retrain and device recovery >> >> Signed-off-by: Avinash Roy >> Signed-off-by: Shivaprasad G Bhat >> ---