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From: "Christian König" <deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
To: Monk Liu <Monk.Liu-5C7GfCeVMHo@public.gmane.org>,
	amd-gfx-CC+yJ3UmIYqDUpFQwHEjaQ@public.gmane.org
Subject: Re: [PATCH] drm/amdgpu:impl vgt_flush for VI(V3)
Date: Mon, 14 Nov 2016 14:04:50 +0100	[thread overview]
Message-ID: <7308be85-4449-4b96-8a32-e6921782c2df@vodafone.de> (raw)
In-Reply-To: <1479127939-17570-1-git-send-email-Monk.Liu-5C7GfCeVMHo@public.gmane.org>

Am 14.11.2016 um 13:52 schrieb Monk Liu:
> when shadowing enabled, tesselation app will trigger
> vm fault because below three tesselation registers:
>
> VGT_TF_RING_SIZE__CI__VI,
> VGT_HS_OFFCHIP_PARAM__CI__VI,
> VGT_TF_MEMORY_BASE__CI__VI,
>
> need to be programed after vgt-flush.
>
> Tesselation picture vm fault disappeared after vgt-flush
> introduced.
>
> v2:implement vgt-flush for CI & SI.
> v3:move vgt flush inside of cntx_cntrl
>
> Change-Id: I77d87d93ce6580e559e734fb41d97ee8c59d245b
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>

We also need to increase the DW estimation for the three gfx engines.

With that fixed the patch is Reviewed-by: Christian König 
<christian.koenig@amd.com>.

> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |  9 +++++++++
>   drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 13 +++++++++++++
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 13 +++++++++++++
>   3 files changed, 35 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> index 9423501..0aacd36 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
> @@ -1463,6 +1463,13 @@ static void gfx_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>   	amdgpu_ring_write(ring, 0x1);
>   }
>   
> +static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
> +{
> +	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
> +	amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
> +		EVENT_INDEX(0));
> +}
> +
>   /**
>    * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
>    *
> @@ -2802,6 +2809,8 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>   
>   static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
>   {
> +	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
> +		gfx_v6_0_ring_emit_vgt_flush(ring);
>   	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
>   	amdgpu_ring_write(ring, 0x80000000);
>   	amdgpu_ring_write(ring, 0);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> index bd9a6c8..493d889 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
> @@ -2105,6 +2105,18 @@ static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>   	amdgpu_ring_write(ring, 0x20); /* poll interval */
>   }
>   
> +static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
> +{
> +	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
> +	amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
> +		EVENT_INDEX(4));
> +
> +	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
> +	amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
> +		EVENT_INDEX(0));
> +}
> +
> +
>   /**
>    * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp
>    *
> @@ -2260,6 +2272,7 @@ static void gfx_v7_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
>   
>   	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
>   	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
> +		gfx_v7_0_ring_emit_vgt_flush(ring);
>   		/* set load_global_config & load_global_uconfig */
>   		dw2 |= 0x8001;
>   		/* set load_cs_sh_regs */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 9017803..d52f458 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -6187,6 +6187,18 @@ static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
>   	amdgpu_ring_write(ring, 0x20); /* poll interval */
>   }
>   
> +static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
> +{
> +	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
> +	amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) |
> +		EVENT_INDEX(4));
> +
> +	amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
> +	amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
> +		EVENT_INDEX(0));
> +}
> +
> +
>   static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
>   {
>   	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> @@ -6372,6 +6384,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
>   
>   	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
>   	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
> +		gfx_v8_0_ring_emit_vgt_flush(ring);
>   		/* set load_global_config & load_global_uconfig */
>   		dw2 |= 0x8001;
>   		/* set load_cs_sh_regs */


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  parent reply	other threads:[~2016-11-14 13:04 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-14 12:52 [PATCH] drm/amdgpu:impl vgt_flush for VI(V3) Monk Liu
     [not found] ` <1479127939-17570-1-git-send-email-Monk.Liu-5C7GfCeVMHo@public.gmane.org>
2016-11-14 13:04   ` Christian König [this message]
2016-11-14 15:53   ` Deucher, Alexander

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