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X-CSE-ConnectionGUID: F3WV4hzVQR6UcDgqfVR5WQ== X-CSE-MsgGUID: ieGBFDedSYeTg/0+z8/TRw== X-IronPort-AV: E=McAfee;i="6700,10204,11383"; a="54229801" X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="54229801" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:05:50 -0700 X-CSE-ConnectionGUID: hPJMrlbWRneuwdv8CFBM3g== X-CSE-MsgGUID: mLbWTvKnSjK5/IiIFlZfFA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,272,1736841600"; d="scan'208";a="129107999" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.251]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Mar 2025 06:05:44 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Mon, 24 Mar 2025 15:05:41 +0200 (EET) To: Richard Zhu cc: frank.li@nxp.com, l.stach@pengutronix.de, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, LKML Subject: Re: [PATCH v1 1/5] PCI: imx6: Start link directly when workaround is not required In-Reply-To: <20250324062647.1891896-2-hongxing.zhu@nxp.com> Message-ID: <73205114-bdb5-2995-e00a-7df7046ea91d@linux.intel.com> References: <20250324062647.1891896-1-hongxing.zhu@nxp.com> <20250324062647.1891896-2-hongxing.zhu@nxp.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Mon, 24 Mar 2025, Richard Zhu wrote: > The current link setup procedure is more like one workaround to detect > the device behind PCIe switches on some i.MX6 platforms. > > To describe more accurately, change the flag name from > IMX_PCIE_FLAG_IMX_SPEED_CHANGE to IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND. > > Then, start PCIe link directly when this flag is not set on i.MX7 or > later paltforms to simple and speed up link training. > > Signed-off-by: Richard Zhu > --- > drivers/pci/controller/dwc/pci-imx6.c | 34 +++++++++++---------------- > 1 file changed, 14 insertions(+), 20 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index c1f7904e3600..aa5c3f235995 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -91,7 +91,7 @@ enum imx_pcie_variants { > }; > > #define IMX_PCIE_FLAG_IMX_PHY BIT(0) > -#define IMX_PCIE_FLAG_IMX_SPEED_CHANGE BIT(1) > +#define IMX_PCIE_FLAG_SPEED_CHANGE_WORDAROUND BIT(1) WORDaround ?? :-) -- i. > #define IMX_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2) > #define IMX_PCIE_FLAG_HAS_PHYDRV BIT(3) > #define IMX_PCIE_FLAG_HAS_APP_RESET BIT(4) > @@ -860,6 +860,12 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > u32 tmp; > int ret; > > + if (!(imx_pcie->drvdata->flags & > + IMX_PCIE_FLAG_SPEED_CHANGE_WORDAROUND)) { > + imx_pcie_ltssm_enable(dev); > + return 0; > + } > + > /* > * Force Gen1 operation when starting the link. In case the link is > * started in Gen2 mode, there is a possibility the devices on the > @@ -896,22 +902,10 @@ static int imx_pcie_start_link(struct dw_pcie *pci) > dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); > dw_pcie_dbi_ro_wr_dis(pci); > > - if (imx_pcie->drvdata->flags & > - IMX_PCIE_FLAG_IMX_SPEED_CHANGE) { > - > - /* > - * On i.MX7, DIRECT_SPEED_CHANGE behaves differently > - * from i.MX6 family when no link speed transition > - * occurs and we go Gen1 -> yep, Gen1. The difference > - * is that, in such case, it will not be cleared by HW > - * which will cause the following code to report false > - * failure. > - */ > - ret = imx_pcie_wait_for_speed_change(imx_pcie); > - if (ret) { > - dev_err(dev, "Failed to bring link up!\n"); > - goto err_reset_phy; > - } > + ret = imx_pcie_wait_for_speed_change(imx_pcie); > + if (ret) { > + dev_err(dev, "Failed to bring link up!\n"); > + goto err_reset_phy; > } > > /* Make sure link training is finished as well! */ > @@ -1665,7 +1659,7 @@ static const struct imx_pcie_drvdata drvdata[] = { > [IMX6Q] = { > .variant = IMX6Q, > .flags = IMX_PCIE_FLAG_IMX_PHY | > - IMX_PCIE_FLAG_IMX_SPEED_CHANGE | > + IMX_PCIE_FLAG_SPEED_CHANGE_WORDAROUND | > IMX_PCIE_FLAG_BROKEN_SUSPEND | > IMX_PCIE_FLAG_SUPPORTS_SUSPEND, > .dbi_length = 0x200, > @@ -1681,7 +1675,7 @@ static const struct imx_pcie_drvdata drvdata[] = { > [IMX6SX] = { > .variant = IMX6SX, > .flags = IMX_PCIE_FLAG_IMX_PHY | > - IMX_PCIE_FLAG_IMX_SPEED_CHANGE | > + IMX_PCIE_FLAG_SPEED_CHANGE_WORDAROUND | > IMX_PCIE_FLAG_SUPPORTS_SUSPEND, > .gpr = "fsl,imx6q-iomuxc-gpr", > .ltssm_off = IOMUXC_GPR12, > @@ -1696,7 +1690,7 @@ static const struct imx_pcie_drvdata drvdata[] = { > [IMX6QP] = { > .variant = IMX6QP, > .flags = IMX_PCIE_FLAG_IMX_PHY | > - IMX_PCIE_FLAG_IMX_SPEED_CHANGE | > + IMX_PCIE_FLAG_SPEED_CHANGE_WORDAROUND | > IMX_PCIE_FLAG_SUPPORTS_SUSPEND, > .dbi_length = 0x200, > .gpr = "fsl,imx6q-iomuxc-gpr", >