diff -r d364becfb083 xen/drivers/passthrough/amd/iommu_map.c
--- a/xen/drivers/passthrough/amd/iommu_map.c	Thu Sep 20 13:31:19 2012 +0200
+++ b/xen/drivers/passthrough/amd/iommu_map.c	Mon Sep 24 10:35:15 2012 +0200
@@ -795,7 +795,8 @@
 
         /* When sharing p2m with iommu, paging mode = 4 */
         hd->paging_mode = IOMMU_PAGING_MODE_LEVEL_4;
-        AMD_IOMMU_DEBUG("Share p2m table with iommu: p2m table = 0x%lx\n",
+        AMD_IOMMU_DEBUG("Share p2m table with iommu: domain:%d p2m table = 0x%lx\n",
+                        d->domain_id,
                         mfn_x(pgd_mfn));
     }
 }
diff -r d364becfb083 xen/drivers/passthrough/amd/pci_amd_iommu.c
--- a/xen/drivers/passthrough/amd/pci_amd_iommu.c	Thu Sep 20 13:31:19 2012 +0200
+++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c	Mon Sep 24 10:35:15 2012 +0200
@@ -87,10 +87,11 @@
 {
     void *dte;
     unsigned long flags;
-    int req_id, valid = 1;
+    int req_id, reqa_id,valid = 1;
     int dte_i = 0;
     u8 bus = PCI_BUS(bdf);
     u8 devfn = PCI_DEVFN2(bdf);
+    struct ivrs_mappings *ivrs_mappings;
 
     struct hvm_iommu *hd = domain_hvm_iommu(domain);
 
@@ -120,12 +121,18 @@
             iommu_dte_set_iotlb((u32 *)dte, dte_i);
 
         amd_iommu_flush_device(iommu, req_id);
-
+    ivrs_mappings = get_ivrs_mappings(iommu->seg);
+    reqa_id = get_dma_requestor_id(iommu->seg, bdf);
+    
         AMD_IOMMU_DEBUG("Setup I/O page table: device id = 0x%04x, "
                         "root table = 0x%"PRIx64", "
-                        "domain = %d, paging mode = %d\n", req_id,
+                        "domain = %d, paging mode = %d | %lx %lx %lx %lx\n", req_id,
                         page_to_maddr(hd->root_table),
-                        hd->domain_id, hd->paging_mode);
+                        hd->domain_id, hd->paging_mode,
+    ivrs_mappings[reqa_id].addr_range_start,
+    ivrs_mappings[reqa_id].addr_range_length,
+    ivrs_mappings[bdf].addr_range_start,
+    ivrs_mappings[bdf].addr_range_length);
     }
 
     spin_unlock_irqrestore(&iommu->lock, flags);
@@ -334,8 +341,10 @@
     struct pci_dev *pdev;
     struct amd_iommu *iommu;
     int bdf;
+    int req_id;
     struct hvm_iommu *t = domain_hvm_iommu(target);
-
+    struct ivrs_mappings *ivrs_mappings;
+    
     ASSERT(spin_is_locked(&pcidevs_lock));
     pdev = pci_get_pdev_by_domain(source, seg, bus, devfn);
     if ( !pdev )
@@ -363,10 +372,17 @@
         allocate_domain_resources(t);
 
     amd_iommu_setup_domain_device(target, iommu, bdf);
-    AMD_IOMMU_DEBUG("Re-assign %04x:%02x:%02x.%u from dom%d to dom%d\n",
+    
+    ivrs_mappings = get_ivrs_mappings(seg);
+    req_id = get_dma_requestor_id(seg, bdf);
+    
+    AMD_IOMMU_DEBUG("Re-assign %04x:%02x:%02x.%u from dom%d to dom%d %lx %lx %lx %lx\n",
                     seg, bus, PCI_SLOT(devfn), PCI_FUNC(devfn),
-                    source->domain_id, target->domain_id);
-
+                    source->domain_id, target->domain_id,
+    ivrs_mappings[req_id].addr_range_start,
+    ivrs_mappings[req_id].addr_range_length,
+    ivrs_mappings[bdf].addr_range_start,
+    ivrs_mappings[bdf].addr_range_length);
     return 0;
 }
 
@@ -385,6 +401,13 @@
             ivrs_mappings[req_id].write_permission,
             ivrs_mappings[req_id].read_permission);
     }
+        AMD_IOMMU_DEBUG("amd_iommu_assign_device:"
+                        " d:%d %04x:%02x:%02x.%u %lx %lx\n",
+                        d->domain_id,
+                        seg, bus, PCI_SLOT(devfn),
+                        PCI_FUNC(devfn),
+                        ivrs_mappings[req_id].addr_range_start,
+                        ivrs_mappings[req_id].addr_range_length);
 
     return reassign_device(dom0, d, seg, bus, devfn);
 }