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keydata= xsDiBFk3nEQRBADAEaSw6zC/EJkiwGPXbWtPxl2xCdSoeepS07jW8UgcHNurfHvUzogEq5xk hu507c3BarVjyWCJOylMNR98Yd8VqD9UfmX0Hb8/BrA+Hl6/DB/eqGptrf4BSRwcZQM32aZK 7Pj2XbGWIUrZrd70x1eAP9QE3P79Y2oLrsCgbZJfEwCgvz9JjGmQqQkRiTVzlZVCJYcyGGsD /0tbFCzD2h20ahe8rC1gbb3K3qk+LpBtvjBu1RY9drYk0NymiGbJWZgab6t1jM7sk2vuf0Py O9Hf9XBmK0uE9IgMaiCpc32XV9oASz6UJebwkX+zF2jG5I1BfnO9g7KlotcA/v5ClMjgo6Gl MDY4HxoSRu3i1cqqSDtVlt+AOVBJBACrZcnHAUSuCXBPy0jOlBhxPqRWv6ND4c9PH1xjQ3NP nxJuMBS8rnNg22uyfAgmBKNLpLgAGVRMZGaGoJObGf72s6TeIqKJo/LtggAS9qAUiuKVnygo 3wjfkS9A3DRO+SpU7JqWdsveeIQyeyEJ/8PTowmSQLakF+3fote9ybzd880fSmFuIEJldWxp Y2ggPGpiZXVsaWNoQHN1c2UuY29tPsJgBBMRAgAgBQJZN5xEAhsDBgsJCAcDAgQVAggDBBYC AwECHgECF4AACgkQoDSui/t3IH4J+wCfQ5jHdEjCRHj23O/5ttg9r9OIruwAn3103WUITZee e7Sbg12UgcQ5lv7SzsFNBFk3nEQQCACCuTjCjFOUdi5Nm244F+78kLghRcin/awv+IrTcIWF hUpSs1Y91iQQ7KItirz5uwCPlwejSJDQJLIS+QtJHaXDXeV6NI0Uef1hP20+y8qydDiVkv6l IreXjTb7DvksRgJNvCkWtYnlS3mYvQ9NzS9PhyALWbXnH6sIJd2O9lKS1Mrfq+y0IXCP10eS FFGg+Av3IQeFatkJAyju0PPthyTqxSI4lZYuJVPknzgaeuJv/2NccrPvmeDg6Coe7ZIeQ8Yj t0ARxu2xytAkkLCel1Lz1WLmwLstV30g80nkgZf/wr+/BXJW/oIvRlonUkxv+IbBM3dX2OV8 AmRv1ySWPTP7AAMFB/9PQK/VtlNUJvg8GXj9ootzrteGfVZVVT4XBJkfwBcpC/XcPzldjv+3 HYudvpdNK3lLujXeA5fLOH+Z/G9WBc5pFVSMocI71I8bT8lIAzreg0WvkWg5V2WZsUMlnDL9 mpwIGFhlbM3gfDMs7MPMu8YQRFVdUvtSpaAs8OFfGQ0ia3LGZcjA6Ik2+xcqscEJzNH+qh8V m5jjp28yZgaqTaRbg3M/+MTbMpicpZuqF4rnB0AQD12/3BNWDR6bmh+EkYSMcEIpQmBM51qM EKYTQGybRCjpnKHGOxG0rfFY1085mBDZCH5Kx0cl0HVJuQKC+dV2ZY5AqjcKwAxpE75MLFkr wkkEGBECAAkFAlk3nEQCGwwACgkQoDSui/t3IH7nnwCfcJWUDUFKdCsBH/E5d+0ZnMQi+G0A nAuWpQkjM1ASeQwSHEeAWPgskBQL In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-purgate-ID: tlsNG-d62444/1787054931-C4F47757-2E336DE1/0/0 X-purgate-type: clean X-purgate-size: 4068 On 02.08.2026 15:09, Sergii Dmytruk wrote: > From: Michał Żygowski > > Report TXT capabilities so that dom0 can query the Intel TXT or AMD > SKINIT support information using xl dmesg. Hmm. I first meant to ask: In how far is this extra logging useful, especially as long as we don't use the features just yet? And only then I noticed that I must have paid too little attention here already in v3. Querying through "xl dmesg" is entirely unreliable. Sooner or later the boot messages will scroll off of the ring buffer. Making this a query-able interface also would mean we can't alter any of the messages, should the want/need arise. For AMD the situation is easy: It's part of the featureset / CPU policy exposed via sysctl. The same is true for SMX on Intel, but the further GETSEC output requires some other means to communicate. I wonder whether making this part of the CPU policy would make sense, or whether to introduce a Dom0-only hypervisor-CPUID bit for it, or whether yet something else would be best here. Likely Andrew will have had thoughts on this long before ... Irrespective of the above also a few comments on the patch itself. > --- a/xen/arch/x86/cpu/amd.c > +++ b/xen/arch/x86/cpu/amd.c > @@ -617,6 +617,21 @@ void amd_process_freq(const struct cpuinfo_x86 *c, > *low_mhz = amd_parse_freq(c->family, lo); > } > > +void amd_log_skinit(const struct cpuinfo_x86 *c) > +{ > + /* > + * Run only on BSP and not during resume to report the capability only once. > + */ > + if ( system_state == SYS_STATE_resume || smp_processor_id() ) > + return; If this is BSP-on-boot only, the function really wants to be __init. For that, ... > + printk("CPU: SKINIT capability "); > + if ( !test_bit(X86_FEATURE_SKINIT, &boot_cpu_data.x86_capability) ) > + printk("not supported\n"); > + else > + printk("supported\n"); > +} > + > void cf_check early_init_amd(struct cpuinfo_x86 *c) > { > if (c == &boot_cpu_data) ... use this condition ... > @@ -1325,6 +1340,7 @@ static void cf_check init_amd(struct cpuinfo_x86 *c) > setup_force_cpu_cap(X86_FEATURE_XEN_REP_MOVSB); > > amd_log_freq(c); > + amd_log_skinit(c); ... at the call site (and of course also the other one). Same for the Intel code, obviously. > @@ -620,6 +625,49 @@ static void init_intel_perf(struct cpuinfo_x86 *c) > } > } > > +/* > + * Print out the SMX and TXT capabilties, so that dom0 can determine if the > + * system is DRTM-capable. > + */ > +static void intel_log_smx_txt(void) > +{ > + unsigned long cr4_val, getsec_caps; > + > + /* > + * Run only on BSP and not during resume to report the capability only once. > + */ > + if ( system_state == SYS_STATE_resume || smp_processor_id() ) > + return; > + > + printk("CPU: SMX capability "); > + if ( !test_bit(X86_FEATURE_SMX, &boot_cpu_data.x86_capability) ) > + { > + printk("not supported\n"); > + return; > + } > + printk("supported\n"); > + > + /* Can't run GETSEC without VMX and SMX */ > + if ( !test_bit(X86_FEATURE_VMX, &boot_cpu_data.x86_capability) ) > + return; > + > + cr4_val = read_cr4(); > + if ( !(cr4_val & X86_CR4_SMXE) ) > + write_cr4(cr4_val | X86_CR4_SMXE); > + > + asm volatile ("getsec\n" > + : "=a" (getsec_caps) > + : "a" (GETSEC_CAPABILITIES), "b" (0) :); Nit (style): Bad indentation, missing blanks, unnecessary \n, and stray colon. Overall: asm volatile ( "getsec" : "=a" (getsec_caps) : "a" (GETSEC_CAPABILITIES), "b" (0) ); I further question the need for volatile here. (Like for we have for CPUID, we anyway may want to gain a getsec() wrapper for GETSEC.) > + if ( !(cr4_val & X86_CR4_SMXE) ) > + write_cr4(cr4_val & ~X86_CR4_SMXE); The clearing of SMXE here is pointless, as the if() already guarantees the bit to be clear. Jan